src/arch/alpha/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Kevin Lim
  30  */
  31
  32 #include "arch/alpha/faults.hh"
  33 #include "cpu/thread_context.hh"
  34 #include "cpu/base.hh"
  35 #include "base/trace.hh"
  36 #if FULL_SYSTEM
  37 #include "arch/alpha/ev5.hh"
  38 #else
  39 #include "sim/process.hh"
  40 #include "mem/page_table.hh"
  41 #endif
  42
  43 namespace AlphaISA
  44 {
  45
  46 FaultName MachineCheckFault::_name = "mchk";
  47 FaultVect MachineCheckFault::_vect = 0x0401;
  48 FaultStat MachineCheckFault::_count;
  49
  50 FaultName AlignmentFault::_name = "unalign";
  51 FaultVect AlignmentFault::_vect = 0x0301;
  52 FaultStat AlignmentFault::_count;
  53
  54 FaultName ResetFault::_name = "reset";
  55 FaultVect ResetFault::_vect = 0x0001;
  56 FaultStat ResetFault::_count;
  57
  58 FaultName ArithmeticFault::_name = "arith";
  59 FaultVect ArithmeticFault::_vect = 0x0501;
  60 FaultStat ArithmeticFault::_count;
  61
  62 #if !FULL_SYSTEM
  63 FaultName PageTableFault::_name = "page_table_fault";
  64 FaultVect PageTableFault::_vect = 0x0000;
  65 FaultStat PageTableFault::_count;
  66 #endif
  67
  68 FaultName InterruptFault::_name = "interrupt";
  69 FaultVect InterruptFault::_vect = 0x0101;
  70 FaultStat InterruptFault::_count;
  71
  72 FaultName NDtbMissFault::_name = "dtb_miss_single";
  73 FaultVect NDtbMissFault::_vect = 0x0201;
  74 FaultStat NDtbMissFault::_count;
  75
  76 FaultName PDtbMissFault::_name = "dtb_miss_double";
  77 FaultVect PDtbMissFault::_vect = 0x0281;
  78 FaultStat PDtbMissFault::_count;
  79
  80 FaultName DtbPageFault::_name = "dfault";
  81 FaultVect DtbPageFault::_vect = 0x0381;
  82 FaultStat DtbPageFault::_count;
  83
  84 FaultName DtbAcvFault::_name = "dfault";
  85 FaultVect DtbAcvFault::_vect = 0x0381;
  86 FaultStat DtbAcvFault::_count;
  87
  88 FaultName DtbAlignmentFault::_name = "unalign";
  89 FaultVect DtbAlignmentFault::_vect = 0x0301;
  90 FaultStat DtbAlignmentFault::_count;
  91
  92 FaultName ItbMissFault::_name = "itbmiss";
  93 FaultVect ItbMissFault::_vect = 0x0181;
  94 FaultStat ItbMissFault::_count;
  95
  96 FaultName ItbPageFault::_name = "itbmiss";
  97 FaultVect ItbPageFault::_vect = 0x0181;
  98 FaultStat ItbPageFault::_count;
  99
 100 FaultName ItbAcvFault::_name = "iaccvio";
 101 FaultVect ItbAcvFault::_vect = 0x0081;
 102 FaultStat ItbAcvFault::_count;
 103
 104 FaultName UnimplementedOpcodeFault::_name = "opdec";
 105 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
 106 FaultStat UnimplementedOpcodeFault::_count;
 107
 108 FaultName FloatEnableFault::_name = "fen";
 109 FaultVect FloatEnableFault::_vect = 0x0581;
 110 FaultStat FloatEnableFault::_count;
 111
 112 FaultName PalFault::_name = "pal";
 113 FaultVect PalFault::_vect = 0x2001;
 114 FaultStat PalFault::_count;
 115
 116 FaultName IntegerOverflowFault::_name = "intover";
 117 FaultVect IntegerOverflowFault::_vect = 0x0501;
 118 FaultStat IntegerOverflowFault::_count;
 119
 120 #if FULL_SYSTEM
 121
 122 void AlphaFault::invoke(ThreadContext * tc)
 123 {
 124     FaultBase::invoke(tc);
 125     countStat()++;
 126
 127     // exception restart address
 128     if (setRestartAddress() || !tc->inPalMode())
 129         tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
 130
 131     if (skipFaultingInstruction()) {
 132         // traps...  skip faulting instruction.
 133         tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
 134                    tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
 135     }
 136
 137     tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
 138     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 139 }
 140
 141 void ArithmeticFault::invoke(ThreadContext * tc)
 142 {
 143     FaultBase::invoke(tc);
 144     panic("Arithmetic traps are unimplemented!");
 145 }
 146
 147 void DtbFault::invoke(ThreadContext * tc)
 148 {
 149     // Set fault address and flags.  Even though we're modeling an
 150     // EV5, we use the EV6 technique of not latching fault registers
 151     // on VPTE loads (instead of locking the registers until IPR_VA is
 152     // read, like the EV5).  The EV6 approach is cleaner and seems to
 153     // work with EV5 PAL code, but not the other way around.
 154     if (!tc->misspeculating()
 155         && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
 156         // set VA register with faulting address
 157         tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
 158
 159         // set MM_STAT register flags
 160         tc->setMiscReg(AlphaISA::IPR_MM_STAT,
 161             (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
 162              | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
 163              | (flags & 0x3f)));
 164
 165         // set VA_FORM register with faulting formatted address
 166         tc->setMiscReg(AlphaISA::IPR_VA_FORM,
 167             tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
 168     }
 169
 170     AlphaFault::invoke(tc);
 171 }
 172
 173 void ItbFault::invoke(ThreadContext * tc)
 174 {
 175     if (!tc->misspeculating()) {
 176         tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
 177         tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
 178                        tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
 179                        (AlphaISA::VAddr(pc).vpn() << 3));
 180     }
 181
 182     AlphaFault::invoke(tc);
 183 }
 184
 185 #else //!FULL_SYSTEM
 186
 187 void PageTableFault::invoke(ThreadContext *tc)
 188 {
 189     Process *p = tc->getProcessPtr();
 190
 191     // address is higher than the stack region or in the current stack region
 192     if (vaddr > p->stack_base || vaddr > p->stack_min)
 193         FaultBase::invoke(tc);
 194
 195     // We've accessed the next page
 196     if (vaddr > p->stack_min - PageBytes) {
 197         DPRINTF(Stack,
 198                 "Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
 199                 p->stack_min, p->stack_base, p->stack_min - PageBytes,
 200                 p->stack_base, vaddr);
 201         p->stack_min -= PageBytes;
 202         if (p->stack_base - p->stack_min > 8*1024*1024)
 203             fatal("Over max stack size for one thread\n");
 204         p->pTable->allocate(p->stack_min, PageBytes);
 205     } else {
 206         warn("Page fault on address %#x\n", vaddr);
 207         FaultBase::invoke(tc);
 208     }
 209 }
 210
 211 #endif
 212
 213 } // namespace AlphaISA
 214