2 * Copyright (c) 2006 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __ARCH_ALPHA_INTERRUPT_HH__
33 #define __ARCH_ALPHA_INTERRUPT_HH__
35 #include "arch/alpha/faults.hh"
36 #include "arch/alpha/isa_traits.hh"
37 #include "base/compiler.hh"
38 #include "base/trace.hh"
39 #include "cpu/thread_context.hh"
40 #include "params/AlphaInterrupts.hh"
41 #include "sim/sim_object.hh"
45 class Interrupts : public SimObject
53 uint64_t interrupts[NumInterruptLevels];
57 typedef AlphaInterruptsParams Params;
62 return dynamic_cast<const Params *>(_params);
65 Interrupts(Params * p) : SimObject(p)
67 memset(interrupts, 0, sizeof(interrupts));
73 post(int int_num, int index)
75 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
77 if (int_num < 0 || int_num >= NumInterruptLevels)
78 panic("int_num out of bounds\n");
80 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
81 panic("int_num out of bounds\n");
83 interrupts[int_num] |= 1 << index;
84 intstatus |= (ULL(1) << int_num);
88 clear(int int_num, int index)
90 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
92 if (int_num < 0 || int_num >= NumInterruptLevels)
93 panic("int_num out of bounds\n");
95 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
96 panic("int_num out of bounds\n");
98 interrupts[int_num] &= ~(1 << index);
99 if (interrupts[int_num] == 0)
100 intstatus &= ~(ULL(1) << int_num);
106 DPRINTF(Interrupt, "Interrupts all cleared\n");
108 memset(interrupts, 0, sizeof(interrupts));
113 serialize(std::ostream &os)
115 SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
116 SERIALIZE_SCALAR(intstatus);
120 unserialize(Checkpoint *cp, const std::string §ion)
122 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
123 UNSERIALIZE_SCALAR(intstatus);
127 checkInterrupts(ThreadContext *tc) const
129 return (intstatus != 0) && !(tc->readPC() & 0x3);
133 getInterrupt(ThreadContext *tc)
138 if (tc->readMiscRegNoEffect(IPR_ASTRR))
139 panic("asynchronous traps not implemented\n");
141 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
142 for (int i = INTLEVEL_SOFTWARE_MIN;
143 i < INTLEVEL_SOFTWARE_MAX; i++) {
144 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
145 // See table 4-19 of 21164 hardware reference
146 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
147 summary |= (ULL(1) << i);
152 uint64_t interrupts = intstatus;
154 for (int i = INTLEVEL_EXTERNAL_MIN;
155 i < INTLEVEL_EXTERNAL_MAX; i++) {
156 if (interrupts & (ULL(1) << i)) {
157 // See table 4-19 of 21164 hardware reference
159 summary |= (ULL(1) << i);
164 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
166 newSummary = summary;
168 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
169 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
171 return new InterruptFault;
178 updateIntrInfo(ThreadContext *tc)
181 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
182 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
187 } // namespace AlphaISA
189 #endif // __ARCH_ALPHA_INTERRUPT_HH__