2 * Copyright (c) 2006 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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28 * Authors: Steve Reinhardt
32 #ifndef __ARCH_ALPHA_INTERRUPT_HH__
33 #define __ARCH_ALPHA_INTERRUPT_HH__
35 #include "arch/alpha/faults.hh"
36 #include "arch/alpha/isa_traits.hh"
37 #include "base/compiler.hh"
38 #include "cpu/thread_context.hh"
50 uint64_t interrupts[NumInterruptLevels];
56 memset(interrupts, 0, sizeof(interrupts));
62 post(int int_num, int index)
64 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
66 if (int_num < 0 || int_num >= NumInterruptLevels)
67 panic("int_num out of bounds\n");
69 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
70 panic("int_num out of bounds\n");
72 interrupts[int_num] |= 1 << index;
73 intstatus |= (ULL(1) << int_num);
77 clear(int int_num, int index)
79 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
81 if (int_num < 0 || int_num >= NumInterruptLevels)
82 panic("int_num out of bounds\n");
84 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
85 panic("int_num out of bounds\n");
87 interrupts[int_num] &= ~(1 << index);
88 if (interrupts[int_num] == 0)
89 intstatus &= ~(ULL(1) << int_num);
95 DPRINTF(Interrupt, "Interrupts all cleared\n");
97 memset(interrupts, 0, sizeof(interrupts));
102 serialize(std::ostream &os)
104 SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
105 SERIALIZE_SCALAR(intstatus);
109 unserialize(Checkpoint *cp, const std::string §ion)
111 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
112 UNSERIALIZE_SCALAR(intstatus);
116 check_interrupts(ThreadContext *tc) const
118 return (intstatus != 0) && !(tc->readPC() & 0x3);
122 getInterrupt(ThreadContext *tc)
127 if (tc->readMiscRegNoEffect(IPR_ASTRR))
128 panic("asynchronous traps not implemented\n");
130 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
131 for (int i = INTLEVEL_SOFTWARE_MIN;
132 i < INTLEVEL_SOFTWARE_MAX; i++) {
133 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
134 // See table 4-19 of 21164 hardware reference
135 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
136 summary |= (ULL(1) << i);
141 uint64_t interrupts = intstatus;
143 for (int i = INTLEVEL_EXTERNAL_MIN;
144 i < INTLEVEL_EXTERNAL_MAX; i++) {
145 if (interrupts & (ULL(1) << i)) {
146 // See table 4-19 of 21164 hardware reference
148 summary |= (ULL(1) << i);
153 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
155 newSummary = summary;
157 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
158 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
160 return new InterruptFault;
167 updateIntrInfo(ThreadContext *tc)
170 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
171 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
178 panic("Shouldn't be called for Alpha\n");
183 } // namespace AlphaISA
185 #endif // __ARCH_ALPHA_INTERRUPT_HH__