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34 #include "arch/alpha/ipr.hh"
38 md_ipr_names MiscRegIndexToIpr
[NumInternalProcRegs
] =
41 IPR_HWINT_CLR
, // H/W interrupt clear register
42 IPR_SL_XMIT
, // serial line transmit register
44 IPR_IC_FLUSH
, // instruction cache flush control
45 IPR_ALT_MODE
, // alternate mode register
46 IPR_DTB_IA
, // DTLB invalidate all register
47 IPR_DTB_IAP
, // DTLB invalidate all process register
48 IPR_ITB_IA
, // ITLB invalidate all register
49 IPR_ITB_IAP
, // ITLB invalidate all process register
52 IPR_INTID
, // interrupt ID register
53 IPR_SL_RCV
, // serial line receive register
54 IPR_MM_STAT
, // data MMU fault status register
55 IPR_ITB_PTE_TEMP
, // ITLB page table entry temp register
56 IPR_DTB_PTE_TEMP
, // DTLB page table entry temporary register
58 IPR_ISR
, // interrupt summary register
59 IPR_ITB_TAG
, // ITLB tag register
60 IPR_ITB_PTE
, // ITLB page table entry register
61 IPR_ITB_ASN
, // ITLB address space register
62 IPR_ITB_IS
, // ITLB invalidate select register
63 IPR_SIRR
, // software interrupt request register
64 IPR_ASTRR
, // asynchronous system trap request register
65 IPR_ASTER
, // asynchronous system trap enable register
66 IPR_EXC_ADDR
, // exception address register
67 IPR_EXC_SUM
, // exception summary register
68 IPR_EXC_MASK
, // exception mask register
69 IPR_PAL_BASE
, // PAL base address register
70 IPR_ICM
, // instruction current mode
71 IPR_IPLR
, // interrupt priority level register
72 IPR_IFAULT_VA_FORM
, // formatted faulting virtual addr register
73 IPR_IVPTBR
, // virtual page table base register
74 IPR_ICSR
, // instruction control and status register
75 IPR_IC_PERR_STAT
, // inst cache parity error status register
76 IPR_PMCTR
, // performance counter register
78 // PAL temporary registers...
79 // register meanings gleaned from osfpal.s source code
80 IPR_PALtemp0
, // local scratch
81 IPR_PALtemp1
, // local scratch
82 IPR_PALtemp2
, // entUna
83 IPR_PALtemp3
, // CPU specific impure area pointer
84 IPR_PALtemp4
, // memory management temp
85 IPR_PALtemp5
, // memory management temp
86 IPR_PALtemp6
, // memory management temp
87 IPR_PALtemp7
, // entIF
88 IPR_PALtemp8
, // intmask
89 IPR_PALtemp9
, // entSys
91 IPR_PALtemp11
, // entInt
92 IPR_PALtemp12
, // entArith
93 IPR_PALtemp13
, // reserved for platform specific PAL
94 IPR_PALtemp14
, // reserved for platform specific PAL
95 IPR_PALtemp15
, // reserved for platform specific PAL
96 IPR_PALtemp16
, // scratch / whami<7:0> / mces<4:0>
97 IPR_PALtemp17
, // sysval
100 IPR_PALtemp20
, // PTBR
101 IPR_PALtemp21
, // entMM
102 IPR_PALtemp22
, // kgp
103 IPR_PALtemp23
, // PCBB
105 IPR_DTB_ASN
, // DTLB address space number register
106 IPR_DTB_CM
, // DTLB current mode register
107 IPR_DTB_TAG
, // DTLB tag register
108 IPR_DTB_PTE
, // DTLB page table entry register
110 IPR_VA
, // fault virtual address register
111 IPR_VA_FORM
, // formatted virtual address register
112 IPR_MVPTBR
, // MTU virtual page table base register
113 IPR_DTB_IS
, // DTLB invalidate single register
114 IPR_CC
, // cycle counter register
115 IPR_CC_CTL
, // cycle counter control register
116 IPR_MCSR
, // MTU control register
118 IPR_DC_PERR_STAT
, // Dcache parity error status register
119 IPR_DC_TEST_CTL
, // Dcache test tag control register
120 IPR_DC_TEST_TAG
, // Dcache test tag register
121 IPR_DC_TEST_TAG_TEMP
, // Dcache test tag temporary register
122 IPR_DC_MODE
, // Dcache mode register
123 IPR_MAF_MODE
// miss address file mode register
126 int IprToMiscRegIndex
[MaxInternalProcRegs
];
128 void initializeIprTable()
130 static bool initialized
= false;
134 memset(IprToMiscRegIndex
, -1, MaxInternalProcRegs
* sizeof(int));
136 for(int x
= 0; x
< NumInternalProcRegs
; x
++)
137 IprToMiscRegIndex
[MiscRegIndexToIpr
[x
]] = x
;