2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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28 * Authors: Steve Reinhardt
32 #ifndef __ARCH_ALPHA_IPR_HH__
33 #define __ARCH_ALPHA_IPR_HH__
37 ////////////////////////////////////////////////////////////////////////
39 // Internal Processor Reigsters
43 RAW_IPR_ISR = 0x100, // interrupt summary register
44 RAW_IPR_ITB_TAG = 0x101, // ITLB tag register
45 RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register
46 RAW_IPR_ITB_ASN = 0x103, // ITLB address space register
47 RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
48 RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register
49 RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
50 RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register
51 RAW_IPR_SIRR = 0x108, // software interrupt request register
52 RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register
53 RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register
54 RAW_IPR_EXC_ADDR = 0x10b, // exception address register
55 RAW_IPR_EXC_SUM = 0x10c, // exception summary register
56 RAW_IPR_EXC_MASK = 0x10d, // exception mask register
57 RAW_IPR_PAL_BASE = 0x10e, // PAL base address register
58 RAW_IPR_ICM = 0x10f, // instruction current mode
59 RAW_IPR_IPLR = 0x110, // interrupt priority level register
60 RAW_IPR_INTID = 0x111, // interrupt ID register
61 RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
62 RAW_IPR_IVPTBR = 0x113, // virtual page table base register
63 RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
64 RAW_IPR_SL_XMIT = 0x116, // serial line transmit register
65 RAW_IPR_SL_RCV = 0x117, // serial line receive register
66 RAW_IPR_ICSR = 0x118, // instruction control and status register
67 RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
68 RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
69 RAW_IPR_PMCTR = 0x11c, // performance counter register
71 // PAL temporary registers...
72 // register meanings gleaned from osfpal.s source code
73 RAW_IPR_PALtemp0 = 0x140, // local scratch
74 RAW_IPR_PALtemp1 = 0x141, // local scratch
75 RAW_IPR_PALtemp2 = 0x142, // entUna
76 RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
77 RAW_IPR_PALtemp4 = 0x144, // memory management temp
78 RAW_IPR_PALtemp5 = 0x145, // memory management temp
79 RAW_IPR_PALtemp6 = 0x146, // memory management temp
80 RAW_IPR_PALtemp7 = 0x147, // entIF
81 RAW_IPR_PALtemp8 = 0x148, // intmask
82 RAW_IPR_PALtemp9 = 0x149, // entSys
83 RAW_IPR_PALtemp10 = 0x14a, // ??
84 RAW_IPR_PALtemp11 = 0x14b, // entInt
85 RAW_IPR_PALtemp12 = 0x14c, // entArith
86 RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
87 RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
88 RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
89 RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
90 RAW_IPR_PALtemp17 = 0x151, // sysval
91 RAW_IPR_PALtemp18 = 0x152, // usp
92 RAW_IPR_PALtemp19 = 0x153, // ksp
93 RAW_IPR_PALtemp20 = 0x154, // PTBR
94 RAW_IPR_PALtemp21 = 0x155, // entMM
95 RAW_IPR_PALtemp22 = 0x156, // kgp
96 RAW_IPR_PALtemp23 = 0x157, // PCBB
98 RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register
99 RAW_IPR_DTB_CM = 0x201, // DTLB current mode register
100 RAW_IPR_DTB_TAG = 0x202, // DTLB tag register
101 RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register
102 RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
104 RAW_IPR_MM_STAT = 0x205, // data MMU fault status register
105 RAW_IPR_VA = 0x206, // fault virtual address register
106 RAW_IPR_VA_FORM = 0x207, // formatted virtual address register
107 RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register
108 RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
109 RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register
110 RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register
111 RAW_IPR_ALT_MODE = 0x20c, // alternate mode register
112 RAW_IPR_CC = 0x20d, // cycle counter register
113 RAW_IPR_CC_CTL = 0x20e, // cycle counter control register
114 RAW_IPR_MCSR = 0x20f, // MTU control register
116 RAW_IPR_DC_FLUSH = 0x210,
117 RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
118 RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
119 RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
120 RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
121 RAW_IPR_DC_MODE = 0x216, // Dcache mode register
122 RAW_IPR_MAF_MODE = 0x217, // miss address file mode register
124 MaxInternalProcRegs // number of IPR registers
131 IPR_HWINT_CLR = MinWriteOnlyIpr,
140 IPR_ITB_IAP = MaxWriteOnlyIpr,
144 IPR_INTID = MinReadOnlyIpr,
149 IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
171 // PAL temporary registers...
172 // register meanings gleaned from osfpal.s source code
214 IPR_DC_TEST_TAG_TEMP,
218 NumInternalProcRegs // number of IPR registers
221 inline bool IprIsWritable(int index)
223 return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
226 inline bool IprIsReadable(int index)
228 return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
231 extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
232 extern int IprToMiscRegIndex[MaxInternalProcRegs];
234 void initializeIprTable();