3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
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17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
31 ////////////////////////////////////////////////////////////////////
33 // Control transfer instructions
39 * Base class for instructions whose disassembly is not purely a
40 * function of the machine instruction (i.e., it depends on the
41 * PC). This class overrides the disassemble() method to check
42 * the PC and symbol table values before re-using a cached
43 * disassembly string. This is necessary for branches and jumps,
44 * where the disassembly string includes the target address (which
45 * may depend on the PC and/or symbol table).
47 class PCDependentDisassembly : public AlphaStaticInst
50 /// Cached program counter from last disassembly
51 mutable Addr cachedPC;
52 /// Cached symbol table pointer from last disassembly
53 mutable const SymbolTable *cachedSymtab;
56 PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
58 : AlphaStaticInst(mnem, _machInst, __opClass),
59 cachedPC(0), cachedSymtab(0)
64 disassemble(Addr pc, const SymbolTable *symtab) const;
68 * Base class for branches (PC-relative control transfers),
69 * conditional or unconditional.
71 class Branch : public PCDependentDisassembly
74 /// Displacement to target address (signed).
78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
79 : PCDependentDisassembly(mnem, _machInst, __opClass),
84 AlphaISA::PCState branchTarget(
85 const AlphaISA::PCState &branchPC) const override;
87 /// Explicitly import the otherwise hidden branchTarget
88 using StaticInst::branchTarget;
90 std::string generateDisassembly(
91 Addr pc, const SymbolTable *symtab) const override;
95 * Base class for jumps (register-indirect control transfers). In
96 * the Alpha ISA, these are always unconditional.
98 class Jump : public PCDependentDisassembly
102 /// Displacement to target address (signed).
107 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
108 : PCDependentDisassembly(mnem, _machInst, __opClass),
113 AlphaISA::PCState branchTarget(ThreadContext *tc) const override;
115 /// Explicitly import the otherwise hidden branchTarget
116 using StaticInst::branchTarget;
118 std::string generateDisassembly(
119 Addr pc, const SymbolTable *symtab) const override;
125 Branch::branchTarget(const AlphaISA::PCState &branchPC) const
127 return branchPC.pc() + 4 + disp;
131 Jump::branchTarget(ThreadContext *tc) const
133 PCState pc = tc->pcState();
134 uint64_t Rb = tc->readIntReg(_srcRegIdx[0].index());
135 pc.set((Rb & ~3) | (pc.pc() & 1));
140 PCDependentDisassembly::disassemble(Addr pc,
141 const SymbolTable *symtab) const
143 if (!cachedDisassembly ||
144 pc != cachedPC || symtab != cachedSymtab)
146 if (cachedDisassembly)
147 delete cachedDisassembly;
150 new std::string(generateDisassembly(pc, symtab));
152 cachedSymtab = symtab;
155 return *cachedDisassembly;
159 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
161 std::stringstream ss;
163 ccprintf(ss, "%-10s ", mnemonic);
165 // There's only one register arg (RA), but it could be
166 // either a source (the condition for conditional
167 // branches) or a destination (the link reg for
168 // unconditional branches)
169 if (_numSrcRegs > 0) {
170 printReg(ss, _srcRegIdx[0]);
173 else if (_numDestRegs > 0) {
174 printReg(ss, _destRegIdx[0]);
178 #ifdef SS_COMPATIBLE_DISASSEMBLY
179 if (_numSrcRegs == 0 && _numDestRegs == 0) {
185 Addr target = pc + 4 + disp;
188 if (symtab && symtab->findSymbol(target, str))
191 ccprintf(ss, "0x%x", target);
197 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
199 std::stringstream ss;
201 ccprintf(ss, "%-10s ", mnemonic);
203 #ifdef SS_COMPATIBLE_DISASSEMBLY
204 if (_numDestRegs == 0) {
210 if (_numDestRegs > 0) {
211 printReg(ss, _destRegIdx[0]);
215 ccprintf(ss, "(r%d)", RB);
221 def template JumpOrBranchDecode {{
223 ? (StaticInst *)new %(class_name)s(machInst)
224 : (StaticInst *)new %(class_name)sAndLink(machInst);
227 def format CondBranch(code) {{
235 ''' % { "code" : code }
236 iop = InstObjParams(name, Name, 'Branch', code,
237 ('IsDirectControl', 'IsCondControl'))
238 header_output = BasicDeclare.subst(iop)
239 decoder_output = BasicConstructor.subst(iop)
240 decode_block = BasicDecode.subst(iop)
241 exec_output = BasicExecute.subst(iop)
245 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
246 # Declare basic control transfer w/o link (i.e. link reg is R31)
247 nolink_code = 'NPC = %s;\n' % npc_expr
248 nolink_iop = InstObjParams(name, Name, base_class,
250 header_output = BasicDeclare.subst(nolink_iop)
251 decoder_output = BasicConstructor.subst(nolink_iop)
252 exec_output = BasicExecute.subst(nolink_iop)
254 # Generate declaration of '*AndLink' version, append to decls
255 link_code = 'Ra = NPC & ~3;\n' + nolink_code
256 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
258 header_output += BasicDeclare.subst(link_iop)
259 decoder_output += BasicConstructor.subst(link_iop)
260 exec_output += BasicExecute.subst(link_iop)
262 # need to use link_iop for the decode template since it is expecting
263 # the shorter version of class_name (w/o "AndLink")
265 return (header_output, decoder_output,
266 JumpOrBranchDecode.subst(nolink_iop), exec_output)
269 def format UncondBranch(*flags) {{
270 flags += ('IsUncondControl', 'IsDirectControl')
271 (header_output, decoder_output, decode_block, exec_output) = \
272 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
275 def format Jump(*flags) {{
276 flags += ('IsUncondControl', 'IsIndirectControl')
277 (header_output, decoder_output, decode_block, exec_output) = \
278 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)