3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
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15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
31 ////////////////////////////////////////////////////////////////////
33 // Control transfer instructions
39 * Base class for instructions whose disassembly is not purely a
40 * function of the machine instruction (i.e., it depends on the
41 * PC). This class overrides the disassemble() method to check
42 * the PC and symbol table values before re-using a cached
43 * disassembly string. This is necessary for branches and jumps,
44 * where the disassembly string includes the target address (which
45 * may depend on the PC and/or symbol table).
47 class PCDependentDisassembly : public AlphaStaticInst
50 /// Cached program counter from last disassembly
51 mutable Addr cachedPC;
52 /// Cached symbol table pointer from last disassembly
53 mutable const SymbolTable *cachedSymtab;
56 PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
58 : AlphaStaticInst(mnem, _machInst, __opClass),
59 cachedPC(0), cachedSymtab(0)
64 disassemble(Addr pc, const SymbolTable *symtab) const;
68 * Base class for branches (PC-relative control transfers),
69 * conditional or unconditional.
71 class Branch : public PCDependentDisassembly
74 /// Displacement to target address (signed).
78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
79 : PCDependentDisassembly(mnem, _machInst, __opClass),
84 Addr branchTarget(Addr branchPC) const;
87 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91 * Base class for jumps (register-indirect control transfers). In
92 * the Alpha ISA, these are always unconditional.
94 class Jump : public PCDependentDisassembly
98 /// Displacement to target address (signed).
103 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
104 : PCDependentDisassembly(mnem, _machInst, __opClass),
109 Addr branchTarget(ThreadContext *tc) const;
112 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
118 Branch::branchTarget(Addr branchPC) const
120 return branchPC + 4 + disp;
124 Jump::branchTarget(ThreadContext *tc) const
126 Addr NPC = tc->readPC() + 4;
127 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
128 return (Rb & ~3) | (NPC & 1);
132 PCDependentDisassembly::disassemble(Addr pc,
133 const SymbolTable *symtab) const
135 if (!cachedDisassembly ||
136 pc != cachedPC || symtab != cachedSymtab)
138 if (cachedDisassembly)
139 delete cachedDisassembly;
142 new std::string(generateDisassembly(pc, symtab));
144 cachedSymtab = symtab;
147 return *cachedDisassembly;
151 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
153 std::stringstream ss;
155 ccprintf(ss, "%-10s ", mnemonic);
157 // There's only one register arg (RA), but it could be
158 // either a source (the condition for conditional
159 // branches) or a destination (the link reg for
160 // unconditional branches)
161 if (_numSrcRegs > 0) {
162 printReg(ss, _srcRegIdx[0]);
165 else if (_numDestRegs > 0) {
166 printReg(ss, _destRegIdx[0]);
170 #ifdef SS_COMPATIBLE_DISASSEMBLY
171 if (_numSrcRegs == 0 && _numDestRegs == 0) {
177 Addr target = pc + 4 + disp;
180 if (symtab && symtab->findSymbol(target, str))
183 ccprintf(ss, "0x%x", target);
189 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
191 std::stringstream ss;
193 ccprintf(ss, "%-10s ", mnemonic);
195 #ifdef SS_COMPATIBLE_DISASSEMBLY
196 if (_numDestRegs == 0) {
202 if (_numDestRegs > 0) {
203 printReg(ss, _destRegIdx[0]);
207 ccprintf(ss, "(r%d)", RB);
213 def template JumpOrBranchDecode {{
215 ? (StaticInst *)new %(class_name)s(machInst)
216 : (StaticInst *)new %(class_name)sAndLink(machInst);
219 def format CondBranch(code) {{
220 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
221 iop = InstObjParams(name, Name, 'Branch', code,
222 ('IsDirectControl', 'IsCondControl'))
223 header_output = BasicDeclare.subst(iop)
224 decoder_output = BasicConstructor.subst(iop)
225 decode_block = BasicDecode.subst(iop)
226 exec_output = BasicExecute.subst(iop)
230 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
231 # Declare basic control transfer w/o link (i.e. link reg is R31)
232 nolink_code = 'NPC = %s;\n' % npc_expr
233 nolink_iop = InstObjParams(name, Name, base_class, nolink_code, flags)
234 header_output = BasicDeclare.subst(nolink_iop)
235 decoder_output = BasicConstructor.subst(nolink_iop)
236 exec_output = BasicExecute.subst(nolink_iop)
238 # Generate declaration of '*AndLink' version, append to decls
239 link_code = 'Ra = NPC & ~3;\n' + nolink_code
240 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
242 header_output += BasicDeclare.subst(link_iop)
243 decoder_output += BasicConstructor.subst(link_iop)
244 exec_output += BasicExecute.subst(link_iop)
246 # need to use link_iop for the decode template since it is expecting
247 # the shorter version of class_name (w/o "AndLink")
249 return (header_output, decoder_output,
250 JumpOrBranchDecode.subst(nolink_iop), exec_output)
253 def format UncondBranch(*flags) {{
254 flags += ('IsUncondControl', 'IsDirectControl')
255 (header_output, decoder_output, decode_block, exec_output) = \
256 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
259 def format Jump(*flags) {{
260 flags += ('IsUncondControl', 'IsIndirectControl')
261 (header_output, decoder_output, decode_block, exec_output) = \
262 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)