src/arch/alpha/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2013 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Copyright (c) 2003-2006 The Regents of The University of Michigan
  16 // All rights reserved.
  17 //
  18 // Redistribution and use in source and binary forms, with or without
  19 // modification, are permitted provided that the following conditions are
  20 // met: redistributions of source code must retain the above copyright
  21 // notice, this list of conditions and the following disclaimer;
  22 // redistributions in binary form must reproduce the above copyright
  23 // notice, this list of conditions and the following disclaimer in the
  24 // documentation and/or other materials provided with the distribution;
  25 // neither the name of the copyright holders nor the names of its
  26 // contributors may be used to endorse or promote products derived from
  27 // this software without specific prior written permission.
  28 //
  29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40 //
  41 // Authors: Steve Reinhardt
  42
  43 ////////////////////////////////////////////////////////////////////
  44 //
  45 // The actual decoder specification
  46 //
  47
  48 decode OPCODE default Unknown::unknown() {
  49
  50     format LoadAddress {
  51         0x08: lda({{ Ra = Rb + disp; }});
  52         0x09: ldah({{ Ra = Rb + (disp << 16); }});
  53     }
  54
  55     format LoadOrNop {
  56         0x0a: ldbu({{ Ra_uq = Mem_ub; }});
  57         0x0c: ldwu({{ Ra_uq = Mem_uw; }});
  58         0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
  59         0x23: ldt({{ Fa = Mem_df; }});
  60         0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
  61         0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
  62     }
  63
  64     format LoadOrPrefetch {
  65         0x28: ldl({{ Ra_sl = Mem_sl; }});
  66         0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
  67         // IsFloating flag on lds gets the prefetch to disassemble
  68         // using f31 instead of r31... funcitonally it's unnecessary
  69         0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
  70                   pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
  71     }
  72
  73     format Store {
  74         0x0e: stb({{ Mem_ub = Ra<7:0>; }});
  75         0x0d: stw({{ Mem_uw = Ra<15:0>; }});
  76         0x2c: stl({{ Mem_ul = Ra<31:0>; }});
  77         0x2d: stq({{ Mem_uq = Ra_uq; }});
  78         0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
  79         0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
  80         0x27: stt({{ Mem_df = Fa; }});
  81     }
  82
  83     format StoreCond {
  84         0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
  85                     {{
  86                         uint64_t tmp = write_result;
  87                         // see stq_c
  88                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
  89                         if (tmp == 1) {
  90                             xc->setStCondFailures(0);
  91                         }
  92                     }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
  93         0x2f: stq_c({{ Mem_uq = Ra; }},
  94                     {{
  95                         uint64_t tmp = write_result;
  96                         // If the write operation returns 0 or 1, then
  97                         // this was a conventional store conditional,
  98                         // and the value indicates the success/failure
  99                         // of the operation.  If another value is
 100                         // returned, then this was a Turbolaser
 101                         // mailbox access, and we don't update the
 102                         // result register at all.
 103                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
 104                         if (tmp == 1) {
 105                             // clear failure counter... this is
 106                             // non-architectural and for debugging
 107                             // only.
 108                             xc->setStCondFailures(0);
 109                         }
 110                     }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
 111     }
 112
 113     format IntegerOperate {
 114
 115         0x10: decode INTFUNC {  // integer arithmetic operations
 116
 117             0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
 118             0x40: addlv({{
 119                 int32_t tmp  = Ra_sl + Rb_or_imm_sl;
 120                 // signed overflow occurs when operands have same sign
 121                 // and sign of result does not match.
 122                 if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
 123                     fault = std::make_shared<IntegerOverflowFault>();
 124                 Rc_sl = tmp;
 125             }});
 126             0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
 127             0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
 128
 129             0x20: addq({{ Rc = Ra + Rb_or_imm; }});
 130             0x60: addqv({{
 131                 uint64_t tmp = Ra + Rb_or_imm;
 132                 // signed overflow occurs when operands have same sign
 133                 // and sign of result does not match.
 134                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
 135                     fault = std::make_shared<IntegerOverflowFault>();
 136                 Rc = tmp;
 137             }});
 138             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
 139             0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
 140
 141             0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
 142             0x49: sublv({{
 143                 int32_t tmp  = Ra_sl - Rb_or_imm_sl;
 144                 // signed overflow detection is same as for add,
 145                 // except we need to look at the *complemented*
 146                 // sign bit of the subtrahend (Rb), i.e., if the initial
 147                 // signs are the *same* then no overflow can occur
 148                 if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
 149                     fault = std::make_shared<IntegerOverflowFault>();
 150                 Rc_sl = tmp;
 151             }});
 152             0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
 153             0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
 154
 155             0x29: subq({{ Rc = Ra - Rb_or_imm; }});
 156             0x69: subqv({{
 157                 uint64_t tmp  = Ra - Rb_or_imm;
 158                 // signed overflow detection is same as for add,
 159                 // except we need to look at the *complemented*
 160                 // sign bit of the subtrahend (Rb), i.e., if the initial
 161                 // signs are the *same* then no overflow can occur
 162                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
 163                     fault = std::make_shared<IntegerOverflowFault>();
 164                 Rc = tmp;
 165             }});
 166             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
 167             0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
 168
 169             0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
 170             0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
 171             0x4d: cmplt({{ Rc = (Ra_sq <  Rb_or_imm_sq); }});
 172             0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
 173             0x1d: cmpult({{ Rc = (Ra_uq <  Rb_or_imm_uq); }});
 174
 175             0x0f: cmpbge({{
 176                 int hi = 7;
 177                 int lo = 0;
 178                 uint64_t tmp = 0;
 179                 for (int i = 0; i < 8; ++i) {
 180                     tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
 181                     hi += 8;
 182                     lo += 8;
 183                 }
 184                 Rc = tmp;
 185             }});
 186         }
 187
 188         0x11: decode INTFUNC {  // integer logical operations
 189
 190             0x00: and({{ Rc = Ra & Rb_or_imm; }});
 191             0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
 192             0x20: bis({{ Rc = Ra | Rb_or_imm; }});
 193             0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
 194             0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
 195             0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
 196
 197             // conditional moves
 198             0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
 199             0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
 200             0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
 201             0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
 202             0x44: cmovlt({{ Rc = (Ra_sq <  0) ? Rb_or_imm : Rc; }});
 203             0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
 204             0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
 205             0x66: cmovgt({{ Rc = (Ra_sq >  0) ? Rb_or_imm : Rc; }});
 206
 207             // For AMASK, RA must be R31.
 208             0x61: decode RA {
 209                 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
 210             }
 211
 212             // For IMPLVER, RA must be R31 and the B operand
 213             // must be the immediate value 1.
 214             0x6c: decode RA {
 215                 31: decode IMM {
 216                     1: decode INTIMM {
 217                         // return EV5 for FullSystem and EV6 otherwise
 218                         1: implver({{ Rc = FullSystem ? 1 : 2 }});
 219                     }
 220                 }
 221             }
 222
 223             // The mysterious 11.25...
 224             0x25: WarnUnimpl::eleven25();
 225         }
 226
 227         0x12: decode INTFUNC {
 228             0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
 229             0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
 230             0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
 231
 232             0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
 233             0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
 234             0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
 235             0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
 236
 237             0x52: mskwh({{
 238                 int bv = Rb_or_imm<2:0>;
 239                 Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
 240             }});
 241             0x62: msklh({{
 242                 int bv = Rb_or_imm<2:0>;
 243                 Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
 244             }});
 245             0x72: mskqh({{
 246                 int bv = Rb_or_imm<2:0>;
 247                 Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
 248             }});
 249
 250             0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
 251             0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
 252             0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
 253             0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
 254
 255             0x5a: extwh({{
 256                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
 257             0x6a: extlh({{
 258                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
 259             0x7a: extqh({{
 260                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
 261
 262             0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
 263             0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
 264             0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
 265             0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
 266
 267             0x57: inswh({{
 268                 int bv = Rb_or_imm<2:0>;
 269                 Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
 270             }});
 271             0x67: inslh({{
 272                 int bv = Rb_or_imm<2:0>;
 273                 Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
 274             }});
 275             0x77: insqh({{
 276                 int bv = Rb_or_imm<2:0>;
 277                 Rc = bv ? (Ra_uq       >> (64 - 8 * bv)) : 0;
 278             }});
 279
 280             0x30: zap({{
 281                 uint64_t zapmask = 0;
 282                 for (int i = 0; i < 8; ++i) {
 283                     if (Rb_or_imm<i:>)
 284                         zapmask |= (mask(8) << (i * 8));
 285                 }
 286                 Rc = Ra & ~zapmask;
 287             }});
 288             0x31: zapnot({{
 289                 uint64_t zapmask = 0;
 290                 for (int i = 0; i < 8; ++i) {
 291                     if (!Rb_or_imm<i:>)
 292                         zapmask |= (mask(8) << (i * 8));
 293                 }
 294                 Rc = Ra & ~zapmask;
 295             }});
 296         }
 297
 298         0x13: decode INTFUNC {  // integer multiplies
 299             0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
 300             0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
 301             0x30: umulh({{
 302                 uint64_t hi, lo;
 303                 mul128(Ra, Rb_or_imm, hi, lo);
 304                 Rc = hi;
 305             }}, IntMultOp);
 306             0x40: mullv({{
 307                 // 32-bit multiply with trap on overflow
 308                 int64_t Rax = Ra_sl;    // sign extended version of Ra_sl
 309                 int64_t Rbx = Rb_or_imm_sl;
 310                 int64_t tmp = Rax * Rbx;
 311                 // To avoid overflow, all the upper 32 bits must match
 312                 // the sign bit of the lower 32.  We code this as
 313                 // checking the upper 33 bits for all 0s or all 1s.
 314                 uint64_t sign_bits = tmp<63:31>;
 315                 if (sign_bits != 0 && sign_bits != mask(33))
 316                     fault = std::make_shared<IntegerOverflowFault>();
 317                 Rc_sl = tmp<31:0>;
 318             }}, IntMultOp);
 319             0x60: mulqv({{
 320                 // 64-bit multiply with trap on overflow
 321                 uint64_t hi, lo;
 322                 mul128(Ra, Rb_or_imm, hi, lo);
 323                 // all the upper 64 bits must match the sign bit of
 324                 // the lower 64
 325                 if (!((hi == 0 && lo<63:> == 0) ||
 326                       (hi == mask(64) && lo<63:> == 1)))
 327                     fault = std::make_shared<IntegerOverflowFault>();
 328                 Rc = lo;
 329             }}, IntMultOp);
 330         }
 331
 332         0x1c: decode INTFUNC {
 333             0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
 334             0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
 335
 336             0x30: ctpop({{
 337                              uint64_t count = 0;
 338                              for (int i = 0; Rb<63:i>; ++i) {
 339                                  if (Rb<i:i> == 0x1)
 340                                      ++count;
 341                              }
 342                              Rc = count;
 343                            }}, IntAluOp);
 344
 345             0x31: perr({{
 346                              uint64_t temp = 0;
 347                              int hi = 7;
 348                              int lo = 0;
 349                              for (int i = 0; i < 8; ++i) {
 350                                  uint8_t ra_ub = Ra_uq<hi:lo>;
 351                                  uint8_t rb_ub = Rb_uq<hi:lo>;
 352                                  temp += (ra_ub >= rb_ub) ?
 353                                          (ra_ub - rb_ub) : (rb_ub - ra_ub);
 354                                  hi += 8;
 355                                  lo += 8;
 356                              }
 357                              Rc = temp;
 358                            }});
 359
 360             0x32: ctlz({{
 361                              uint64_t count = 0;
 362                              uint64_t temp = Rb;
 363                              if (temp<63:32>) temp >>= 32; else count += 32;
 364                              if (temp<31:16>) temp >>= 16; else count += 16;
 365                              if (temp<15:8>) temp >>= 8; else count += 8;
 366                              if (temp<7:4>) temp >>= 4; else count += 4;
 367                              if (temp<3:2>) temp >>= 2; else count += 2;
 368                              if (temp<1:1>) temp >>= 1; else count += 1;
 369                              if ((temp<0:0>) != 0x1) count += 1;
 370                              Rc = count;
 371                            }}, IntAluOp);
 372
 373             0x33: cttz({{
 374                              uint64_t count = 0;
 375                              uint64_t temp = Rb;
 376                              if (!(temp<31:0>)) { temp >>= 32; count += 32; }
 377                              if (!(temp<15:0>)) { temp >>= 16; count += 16; }
 378                              if (!(temp<7:0>)) { temp >>= 8; count += 8; }
 379                              if (!(temp<3:0>)) { temp >>= 4; count += 4; }
 380                              if (!(temp<1:0>)) { temp >>= 2; count += 2; }
 381                              if (!(temp<0:0> & ULL(0x1))) {
 382                                  temp >>= 1; count += 1;
 383                              }
 384                              if (!(temp<0:0> & ULL(0x1))) count += 1;
 385                              Rc = count;
 386                            }}, IntAluOp);
 387
 388
 389             0x34: unpkbw({{
 390                              Rc = (Rb_uq<7:0>
 391                                    | (Rb_uq<15:8> << 16)
 392                                    | (Rb_uq<23:16> << 32)
 393                                    | (Rb_uq<31:24> << 48));
 394                            }}, IntAluOp);
 395
 396             0x35: unpkbl({{
 397                              Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
 398                            }}, IntAluOp);
 399
 400             0x36: pkwb({{
 401                              Rc = (Rb_uq<7:0>
 402                                    | (Rb_uq<23:16> << 8)
 403                                    | (Rb_uq<39:32> << 16)
 404                                    | (Rb_uq<55:48> << 24));
 405                            }}, IntAluOp);
 406
 407             0x37: pklb({{
 408                              Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
 409                            }}, IntAluOp);
 410
 411             0x38: minsb8({{
 412                              uint64_t temp = 0;
 413                              int hi = 63;
 414                              int lo = 56;
 415                              for (int i = 7; i >= 0; --i) {
 416                                  int8_t ra_sb = Ra_uq<hi:lo>;
 417                                  int8_t rb_sb = Rb_uq<hi:lo>;
 418                                  temp = ((temp << 8)
 419                                          | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
 420                                                           : Rb_uq<hi:lo>));
 421                                  hi -= 8;
 422                                  lo -= 8;
 423                              }
 424                              Rc = temp;
 425                           }});
 426
 427             0x39: minsw4({{
 428                              uint64_t temp = 0;
 429                              int hi = 63;
 430                              int lo = 48;
 431                              for (int i = 3; i >= 0; --i) {
 432                                  int16_t ra_sw = Ra_uq<hi:lo>;
 433                                  int16_t rb_sw = Rb_uq<hi:lo>;
 434                                  temp = ((temp << 16)
 435                                          | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
 436                                                           : Rb_uq<hi:lo>));
 437                                  hi -= 16;
 438                                  lo -= 16;
 439                              }
 440                              Rc = temp;
 441                           }});
 442
 443             0x3a: minub8({{
 444                              uint64_t temp = 0;
 445                              int hi = 63;
 446                              int lo = 56;
 447                              for (int i = 7; i >= 0; --i) {
 448                                  uint8_t ra_ub = Ra_uq<hi:lo>;
 449                                  uint8_t rb_ub = Rb_uq<hi:lo>;
 450                                  temp = ((temp << 8)
 451                                          | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
 452                                                           : Rb_uq<hi:lo>));
 453                                  hi -= 8;
 454                                  lo -= 8;
 455                              }
 456                              Rc = temp;
 457                           }});
 458
 459             0x3b: minuw4({{
 460                              uint64_t temp = 0;
 461                              int hi = 63;
 462                              int lo = 48;
 463                              for (int i = 3; i >= 0; --i) {
 464                                  uint16_t ra_sw = Ra_uq<hi:lo>;
 465                                  uint16_t rb_sw = Rb_uq<hi:lo>;
 466                                  temp = ((temp << 16)
 467                                          | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
 468                                                           : Rb_uq<hi:lo>));
 469                                  hi -= 16;
 470                                  lo -= 16;
 471                              }
 472                              Rc = temp;
 473                           }});
 474
 475             0x3c: maxub8({{
 476                              uint64_t temp = 0;
 477                              int hi = 63;
 478                              int lo = 56;
 479                              for (int i = 7; i >= 0; --i) {
 480                                  uint8_t ra_ub = Ra_uq<hi:lo>;
 481                                  uint8_t rb_ub = Rb_uq<hi:lo>;
 482                                  temp = ((temp << 8)
 483                                          | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
 484                                                           : Rb_uq<hi:lo>));
 485                                  hi -= 8;
 486                                  lo -= 8;
 487                              }
 488                              Rc = temp;
 489                           }});
 490
 491             0x3d: maxuw4({{
 492                              uint64_t temp = 0;
 493                              int hi = 63;
 494                              int lo = 48;
 495                              for (int i = 3; i >= 0; --i) {
 496                                  uint16_t ra_uw = Ra_uq<hi:lo>;
 497                                  uint16_t rb_uw = Rb_uq<hi:lo>;
 498                                  temp = ((temp << 16)
 499                                          | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
 500                                                           : Rb_uq<hi:lo>));
 501                                  hi -= 16;
 502                                  lo -= 16;
 503                              }
 504                              Rc = temp;
 505                           }});
 506
 507             0x3e: maxsb8({{
 508                              uint64_t temp = 0;
 509                              int hi = 63;
 510                              int lo = 56;
 511                              for (int i = 7; i >= 0; --i) {
 512                                  int8_t ra_sb = Ra_uq<hi:lo>;
 513                                  int8_t rb_sb = Rb_uq<hi:lo>;
 514                                  temp = ((temp << 8)
 515                                          | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
 516                                                           : Rb_uq<hi:lo>));
 517                                  hi -= 8;
 518                                  lo -= 8;
 519                              }
 520                              Rc = temp;
 521                           }});
 522
 523             0x3f: maxsw4({{
 524                              uint64_t temp = 0;
 525                              int hi = 63;
 526                              int lo = 48;
 527                              for (int i = 3; i >= 0; --i) {
 528                                  int16_t ra_sw = Ra_uq<hi:lo>;
 529                                  int16_t rb_sw = Rb_uq<hi:lo>;
 530                                  temp = ((temp << 16)
 531                                          | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
 532                                                           : Rb_uq<hi:lo>));
 533                                  hi -= 16;
 534                                  lo -= 16;
 535                              }
 536                              Rc = temp;
 537                           }});
 538
 539             format BasicOperateWithNopCheck {
 540                 0x70: decode RB {
 541                     31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
 542                 }
 543                 0x78: decode RB {
 544                     31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
 545                               FloatCvtOp);
 546                 }
 547             }
 548         }
 549     }
 550
 551     // Conditional branches.
 552     format CondBranch {
 553         0x39: beq({{ cond = (Ra == 0); }});
 554         0x3d: bne({{ cond = (Ra != 0); }});
 555         0x3e: bge({{ cond = (Ra_sq >= 0); }});
 556         0x3f: bgt({{ cond = (Ra_sq >  0); }});
 557         0x3b: ble({{ cond = (Ra_sq <= 0); }});
 558         0x3a: blt({{ cond = (Ra_sq < 0); }});
 559         0x38: blbc({{ cond = ((Ra & 1) == 0); }});
 560         0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
 561
 562         0x31: fbeq({{ cond = (Fa == 0); }});
 563         0x35: fbne({{ cond = (Fa != 0); }});
 564         0x36: fbge({{ cond = (Fa >= 0); }});
 565         0x37: fbgt({{ cond = (Fa >  0); }});
 566         0x33: fble({{ cond = (Fa <= 0); }});
 567         0x32: fblt({{ cond = (Fa < 0); }});
 568     }
 569
 570     // unconditional branches
 571     format UncondBranch {
 572         0x30: br();
 573         0x34: bsr(IsCall);
 574     }
 575
 576     // indirect branches
 577     0x1a: decode JMPFUNC {
 578         format Jump {
 579             0: jmp();
 580             1: jsr(IsCall);
 581             2: ret(IsReturn);
 582             3: jsr_coroutine(IsCall, IsReturn);
 583         }
 584     }
 585
 586     // Square root and integer-to-FP moves
 587     0x14: decode FP_SHORTFUNC {
 588         // Integer to FP register moves must have RB == 31
 589         0x4: decode RB {
 590             31: decode FP_FULLFUNC {
 591                 format BasicOperateWithNopCheck {
 592                     0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
 593                     0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
 594                     0x014: FailUnimpl::itoff(); // VAX-format conversion
 595                 }
 596             }
 597         }
 598
 599         // Square root instructions must have FA == 31
 600         0xb: decode FA {
 601             31: decode FP_TYPEFUNC {
 602                 format FloatingPointOperate {
 603 #if SS_COMPATIBLE_FP
 604                     0x0b: sqrts({{
 605                         if (Fb < 0.0)
 606                             fault = std::make_shared<ArithmeticFault>();
 607                         Fc = sqrt(Fb);
 608                     }}, FloatSqrtOp);
 609 #else
 610                     0x0b: sqrts({{
 611                         if (Fb_sf < 0.0)
 612                             fault = std::make_shared<ArithmeticFault>();
 613                         Fc_sf = sqrt(Fb_sf);
 614                     }}, FloatSqrtOp);
 615 #endif
 616                     0x2b: sqrtt({{
 617                         if (Fb < 0.0)
 618                             fault = std::make_shared<ArithmeticFault>();
 619                         Fc = sqrt(Fb);
 620                     }}, FloatSqrtOp);
 621                 }
 622             }
 623         }
 624
 625         // VAX-format sqrtf and sqrtg are not implemented
 626         0xa: FailUnimpl::sqrtfg();
 627     }
 628
 629     // IEEE floating point
 630     0x16: decode FP_SHORTFUNC_TOP2 {
 631         // The top two bits of the short function code break this
 632         // space into four groups: binary ops, compares, reserved, and
 633         // conversions.  See Table 4-12 of AHB.  There are different
 634         // special cases in these different groups, so we decode on
 635         // these top two bits first just to select a decode strategy.
 636         // Most of these instructions may have various trapping and
 637         // rounding mode flags set; these are decoded in the
 638         // FloatingPointDecode template used by the
 639         // FloatingPointOperate format.
 640
 641         // add/sub/mul/div: just decode on the short function code
 642         // and source type.  All valid trapping and rounding modes apply.
 643         0: decode FP_TRAPMODE {
 644             // check for valid trapping modes here
 645             0,1,5,7: decode FP_TYPEFUNC {
 646                    format FloatingPointOperate {
 647 #if SS_COMPATIBLE_FP
 648                        0x00: adds({{ Fc = Fa + Fb; }});
 649                        0x01: subs({{ Fc = Fa - Fb; }});
 650                        0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
 651                        0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
 652 #else
 653                        0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
 654                        0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
 655                        0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
 656                        0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
 657 #endif
 658
 659                        0x20: addt({{ Fc = Fa + Fb; }});
 660                        0x21: subt({{ Fc = Fa - Fb; }});
 661                        0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
 662                        0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
 663                    }
 664              }
 665         }
 666
 667         // Floating-point compare instructions must have the default
 668         // rounding mode, and may use the default trapping mode or
 669         // /SU.  Both trapping modes are treated the same by M5; the
 670         // only difference on the real hardware (as far a I can tell)
 671         // is that without /SU you'd get an imprecise trap if you
 672         // tried to compare a NaN with something else (instead of an
 673         // "unordered" result).
 674         1: decode FP_FULLFUNC {
 675             format BasicOperateWithNopCheck {
 676                 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
 677                                      FloatCmpOp);
 678                 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
 679                                      FloatCmpOp);
 680                 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
 681                                      FloatCmpOp);
 682                 0x0a4, 0x5a4: cmptun({{ // unordered
 683                     Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
 684                 }}, FloatCmpOp);
 685             }
 686         }
 687
 688         // The FP-to-integer and integer-to-FP conversion insts
 689         // require that FA be 31.
 690         3: decode FA {
 691             31: decode FP_TYPEFUNC {
 692                 format FloatingPointOperate {
 693                     0x2f: decode FP_ROUNDMODE {
 694                         format FPFixedRounding {
 695                             // "chopped" i.e. round toward zero
 696                             0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
 697                                      Chopped);
 698                             // round to minus infinity
 699                             1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
 700                                      MinusInfinity);
 701                         }
 702                       default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
 703                     }
 704
 705                     // The cvtts opcode is overloaded to be cvtst if the trap
 706                     // mode is 2 or 6 (which are not valid otherwise)
 707                     0x2c: decode FP_FULLFUNC {
 708                         format BasicOperateWithNopCheck {
 709                             // trap on denorm version "cvtst/s" is
 710                             // simulated same as cvtst
 711                             0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
 712                         }
 713                       default: cvtts({{ Fc_sf = Fb; }});
 714                     }
 715
 716                     // The trapping mode for integer-to-FP conversions
 717                     // must be /SUI or nothing; /U and /SU are not
 718                     // allowed.  The full set of rounding modes are
 719                     // supported though.
 720                     0x3c: decode FP_TRAPMODE {
 721                         0,7: cvtqs({{ Fc_sf = Fb_sq; }});
 722                     }
 723                     0x3e: decode FP_TRAPMODE {
 724                         0,7: cvtqt({{ Fc    = Fb_sq; }});
 725                     }
 726                 }
 727             }
 728         }
 729     }
 730
 731     // misc FP operate
 732     0x17: decode FP_FULLFUNC {
 733         format BasicOperateWithNopCheck {
 734             0x010: cvtlq({{
 735                 Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
 736             }});
 737             0x030: cvtql({{
 738                 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
 739             }});
 740
 741             // We treat the precise & imprecise trapping versions of
 742             // cvtql identically.
 743             0x130, 0x530: cvtqlv({{
 744                 // To avoid overflow, all the upper 32 bits must match
 745                 // the sign bit of the lower 32.  We code this as
 746                 // checking the upper 33 bits for all 0s or all 1s.
 747                 uint64_t sign_bits = Fb_uq<63:31>;
 748                 if (sign_bits != 0 && sign_bits != mask(33))
 749                     fault = std::make_shared<IntegerOverflowFault>();
 750                 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
 751             }});
 752
 753             0x020: cpys({{  // copy sign
 754                 Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
 755             }});
 756             0x021: cpysn({{ // copy sign negated
 757                 Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
 758             }});
 759             0x022: cpyse({{ // copy sign and exponent
 760                 Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
 761             }});
 762
 763             0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
 764             0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
 765             0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
 766             0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
 767             0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
 768             0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
 769
 770             0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
 771             0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
 772         }
 773     }
 774
 775     // miscellaneous mem-format ops
 776     0x18: decode MEMFUNC {
 777         format WarnUnimpl {
 778             0x8000: fetch();
 779             0xa000: fetch_m();
 780             0xe800: ecb();
 781         }
 782
 783         format MiscPrefetch {
 784             0xf800: wh64({{ EA = Rb & ~ULL(63); }},
 785                          {{ ; }},
 786                          mem_flags = PREFETCH);
 787         }
 788
 789         format BasicOperate {
 790             0xc000: rpcc({{
 791                 /* Rb is a fake dependency so here is a fun way to get
 792                  * the parser to understand that.
 793                  */
 794                 uint64_t unused_var M5_VAR_USED = Rb;
 795                 Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
 796             }}, IsUnverifiable);
 797
 798             // All of the barrier instructions below do nothing in
 799             // their execute() methods (hence the empty code blocks).
 800             // All of their functionality is hard-coded in the
 801             // pipeline based on the flags IsSerializing,
 802             // IsMemBarrier, and IsWriteBarrier.  In the current
 803             // detailed CPU model, the execute() function only gets
 804             // called at fetch, so there's no way to generate pipeline
 805             // behavior at any other stage.  Once we go to an
 806             // exec-in-exec CPU model we should be able to get rid of
 807             // these flags and implement this behavior via the
 808             // execute() methods.
 809
 810             // trapb is just a barrier on integer traps, where excb is
 811             // a barrier on integer and FP traps.  "EXCB is thus a
 812             // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
 813             // them the same though.
 814             0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
 815             0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
 816             0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
 817             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
 818         }
 819
 820         0xe000: decode FullSystemInt {
 821             0: FailUnimpl::rc_se();
 822             default: BasicOperate::rc({{
 823                 Ra = IntrFlag;
 824                 IntrFlag = 0;
 825             }}, IsNonSpeculative, IsUnverifiable);
 826         }
 827         0xf000: decode FullSystemInt {
 828             0: FailUnimpl::rs_se();
 829             default: BasicOperate::rs({{
 830                 Ra = IntrFlag;
 831                 IntrFlag = 1;
 832             }}, IsNonSpeculative, IsUnverifiable);
 833         }
 834     }
 835
 836     0x00: decode FullSystemInt {
 837         0: decode PALFUNC {
 838             format EmulatedCallPal {
 839                 0x00: halt ({{
 840                     exitSimLoop("halt instruction encountered");
 841                 }}, IsNonSpeculative);
 842                 0x83: callsys({{
 843                     xc->syscall(R0, &fault);
 844                 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
 845                 // Read uniq reg into ABI return value register (r0)
 846                 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
 847                 // Write uniq reg with value from ABI arg register (r16)
 848                 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
 849             }
 850         }
 851         default: CallPal::call_pal({{
 852             if (!palValid ||
 853                 (palPriv
 854                  && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
 855                 // invalid pal function code, or attempt to do privileged
 856                 // PAL call in non-kernel mode
 857                 fault = std::make_shared<UnimplementedOpcodeFault>();
 858             } else {
 859                 // check to see if simulator wants to do something special
 860                 // on this PAL call (including maybe suppress it)
 861                 bool dopal = xc->simPalCheck(palFunc);
 862
 863                 if (dopal) {
 864                     xc->setMiscReg(IPR_EXC_ADDR, NPC);
 865                     NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
 866                 }
 867             }
 868         }}, IsNonSpeculative);
 869     }
 870
 871     0x1b: decode PALMODE {
 872         0: OpcdecFault::hw_st_quad();
 873         1: decode HW_LDST_QUAD {
 874             format HwLoad {
 875                 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
 876                          L, IsSerializing, IsSerializeBefore);
 877                 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
 878                          Q, IsSerializing, IsSerializeBefore);
 879             }
 880         }
 881     }
 882
 883     0x1f: decode PALMODE {
 884         0: OpcdecFault::hw_st_cond();
 885         format HwStore {
 886             1: decode HW_LDST_COND {
 887                 0: decode HW_LDST_QUAD {
 888                     0: hw_st({{ EA = (Rb + disp) & ~3; }},
 889                 {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
 890                     1: hw_st({{ EA = (Rb + disp) & ~7; }},
 891                 {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
 892                 }
 893
 894                 1: FailUnimpl::hw_st_cond();
 895             }
 896         }
 897     }
 898
 899     0x19: decode PALMODE {
 900         0: OpcdecFault::hw_mfpr();
 901         format HwMoveIPR {
 902             1: hw_mfpr({{
 903                 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
 904                         IprToMiscRegIndex[ipr_index] : -1;
 905                 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
 906                     miscRegIndex >= NumInternalProcRegs)
 907                     fault = std::make_shared<UnimplementedOpcodeFault>();
 908                 else
 909                     Ra = xc->readMiscReg(miscRegIndex);
 910             }}, IsIprAccess);
 911         }
 912     }
 913
 914     0x1d: decode PALMODE {
 915         0: OpcdecFault::hw_mtpr();
 916         format HwMoveIPR {
 917             1: hw_mtpr({{
 918                 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
 919                         IprToMiscRegIndex[ipr_index] : -1;
 920                 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
 921                     miscRegIndex >= NumInternalProcRegs)
 922                     fault = std::make_shared<UnimplementedOpcodeFault>();
 923                 else
 924                     xc->setMiscReg(miscRegIndex, Ra);
 925                 if (traceData) { traceData->setData(Ra); }
 926             }}, IsIprAccess);
 927         }
 928     }
 929
 930   0x1e: decode PALMODE {
 931       0: OpcdecFault::hw_rei();
 932         format BasicOperate {
 933           1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
 934         }
 935     }
 936
 937     format BasicOperate {
 938         // M5 special opcodes use the reserved 0x01 opcode space
 939         0x01: decode M5FUNC {
 940             0x00: arm({{
 941                 PseudoInst::arm(xc->tcBase());
 942             }}, IsNonSpeculative);
 943             0x01: quiesce({{
 944                 // Don't sleep if (unmasked) interrupts are pending
 945                 Interrupts* interrupts =
 946                     xc->tcBase()->getCpuPtr()->getInterruptController(0);
 947                 if (interrupts->checkInterrupts(xc->tcBase())) {
 948                     PseudoInst::quiesceSkip(xc->tcBase());
 949                 } else {
 950                     PseudoInst::quiesce(xc->tcBase());
 951                 }
 952             }}, IsNonSpeculative, IsQuiesce);
 953             0x02: quiesceNs({{
 954                 PseudoInst::quiesceNs(xc->tcBase(), R16);
 955             }}, IsNonSpeculative, IsQuiesce);
 956             0x03: quiesceCycles({{
 957                 PseudoInst::quiesceCycles(xc->tcBase(), R16);
 958             }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
 959             0x04: quiesceTime({{
 960                 R0 = PseudoInst::quiesceTime(xc->tcBase());
 961             }}, IsNonSpeculative, IsUnverifiable);
 962             0x07: rpns({{
 963                 R0 = PseudoInst::rpns(xc->tcBase());
 964             }}, IsNonSpeculative, IsUnverifiable);
 965             0x09: wakeCPU({{
 966                 PseudoInst::wakeCPU(xc->tcBase(), R16);
 967             }}, IsNonSpeculative, IsUnverifiable);
 968             0x10: deprecated_ivlb({{
 969                 warn_once("Obsolete M5 ivlb instruction encountered.\n");
 970             }});
 971             0x11: deprecated_ivle({{
 972                 warn_once("Obsolete M5 ivlb instruction encountered.\n");
 973             }});
 974             0x20: deprecated_exit ({{
 975                 warn_once("deprecated M5 exit instruction encountered.\n");
 976                 PseudoInst::m5exit(xc->tcBase(), 0);
 977             }}, No_OpClass, IsNonSpeculative);
 978             0x21: m5exit({{
 979                 PseudoInst::m5exit(xc->tcBase(), R16);
 980             }}, No_OpClass, IsNonSpeculative);
 981             0x31: loadsymbol({{
 982                 PseudoInst::loadsymbol(xc->tcBase());
 983             }}, No_OpClass, IsNonSpeculative);
 984             0x30: initparam({{
 985                 Ra = PseudoInst::initParam(xc->tcBase(), R16, R17);
 986             }});
 987             0x40: resetstats({{
 988                 PseudoInst::resetstats(xc->tcBase(), R16, R17);
 989             }}, IsNonSpeculative);
 990             0x41: dumpstats({{
 991                 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
 992             }}, IsNonSpeculative);
 993             0x42: dumpresetstats({{
 994                 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
 995             }}, IsNonSpeculative);
 996             0x43: m5checkpoint({{
 997                 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
 998             }}, IsNonSpeculative);
 999             0x50: m5readfile({{
1000                 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
1001             }}, IsNonSpeculative);
1002             0x51: m5break({{
1003                 PseudoInst::debugbreak(xc->tcBase());
1004             }}, IsNonSpeculative);
1005             0x52: m5switchcpu({{
1006                 PseudoInst::switchcpu(xc->tcBase());
1007             }}, IsNonSpeculative);
1008             0x53: m5addsymbol({{
1009                 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
1010             }}, IsNonSpeculative);
1011             0x54: m5panic({{
1012                 panic("M5 panic instruction called at pc = %#x.", PC);
1013             }}, IsNonSpeculative);
1014 #define  CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
1015             0x55: decode RA {
1016                 0x00: m5a_old({{
1017                     panic("Deprecated M5 annotate instruction executed "
1018                           "at pc = %#x\n", PC);
1019                 }}, IsNonSpeculative);
1020                 0x01: m5a_bsm({{
1021                     CPANN(swSmBegin);
1022                 }}, IsNonSpeculative);
1023                 0x02: m5a_esm({{
1024                     CPANN(swSmEnd);
1025                 }}, IsNonSpeculative);
1026                 0x03: m5a_begin({{
1027                     CPANN(swExplictBegin);
1028                 }}, IsNonSpeculative);
1029                 0x04: m5a_end({{
1030                     CPANN(swEnd);
1031                 }}, IsNonSpeculative);
1032                 0x06: m5a_q({{
1033                     CPANN(swQ);
1034                 }}, IsNonSpeculative);
1035                 0x07: m5a_dq({{
1036                     CPANN(swDq);
1037                 }}, IsNonSpeculative);
1038                 0x08: m5a_wf({{
1039                     CPANN(swWf);
1040                 }}, IsNonSpeculative);
1041                 0x09: m5a_we({{
1042                     CPANN(swWe);
1043                 }}, IsNonSpeculative);
1044                 0x0C: m5a_sq({{
1045                     CPANN(swSq);
1046                 }}, IsNonSpeculative);
1047                 0x0D: m5a_aq({{
1048                     CPANN(swAq);
1049                 }}, IsNonSpeculative);
1050                 0x0E: m5a_pq({{
1051                     CPANN(swPq);
1052                 }}, IsNonSpeculative);
1053                 0x0F: m5a_l({{
1054                     CPANN(swLink);
1055                 }}, IsNonSpeculative);
1056                 0x10: m5a_identify({{
1057                     CPANN(swIdentify);
1058                 }}, IsNonSpeculative);
1059                 0x11: m5a_getid({{
1060                     R0 = CPANN(swGetId);
1061                 }}, IsNonSpeculative);
1062                 0x13: m5a_scl({{
1063                     CPANN(swSyscallLink);
1064                 }}, IsNonSpeculative);
1065                 0x14: m5a_rq({{
1066                     CPANN(swRq);
1067                 }}, IsNonSpeculative);
1068             } // M5 Annotate Operations
1069 #undef CPANN
1070             0x56: m5reserved2({{
1071                 warn("M5 reserved opcode ignored");
1072             }}, IsNonSpeculative);
1073             0x57: m5reserved3({{
1074                 warn("M5 reserved opcode ignored");
1075             }}, IsNonSpeculative);
1076             0x58: m5reserved4({{
1077                 warn("M5 reserved opcode ignored");
1078             }}, IsNonSpeculative);
1079             0x59: m5reserved5({{
1080                 warn("M5 reserved opcode ignored");
1081             }}, IsNonSpeculative);
1082         }
1083     }
1084 }