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base: Delete alpha loader components.
[gem5.git] / src / arch / alpha / isa / decoder.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2013 ARM Limited
4 // All rights reserved
5 //
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
14 //
15 // Copyright (c) 2003-2006 The Regents of The University of Michigan
16 // All rights reserved.
17 //
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are
20 // met: redistributions of source code must retain the above copyright
21 // notice, this list of conditions and the following disclaimer;
22 // redistributions in binary form must reproduce the above copyright
23 // notice, this list of conditions and the following disclaimer in the
24 // documentation and/or other materials provided with the distribution;
25 // neither the name of the copyright holders nor the names of its
26 // contributors may be used to endorse or promote products derived from
27 // this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 //
41 // Authors: Steve Reinhardt
42
43 ////////////////////////////////////////////////////////////////////
44 //
45 // The actual decoder specification
46 //
47
48 decode OPCODE default Unknown::unknown() {
49
50 format LoadAddress {
51 0x08: lda({{ Ra = Rb + disp; }});
52 0x09: ldah({{ Ra = Rb + (disp << 16); }});
53 }
54
55 format LoadOrNop {
56 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
57 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
58 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
59 0x23: ldt({{ Fa = Mem_df; }});
60 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
61 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
62 }
63
64 format LoadOrPrefetch {
65 0x28: ldl({{ Ra_sl = Mem_sl; }});
66 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
67 // IsFloating flag on lds gets the prefetch to disassemble
68 // using f31 instead of r31... funcitonally it's unnecessary
69 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
70 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
71 }
72
73 format Store {
74 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
75 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
76 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
77 0x2d: stq({{ Mem_uq = Ra_uq; }});
78 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
79 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
80 0x27: stt({{ Mem_df = Fa; }});
81 }
82
83 format StoreCond {
84 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
85 {{
86 uint64_t tmp = write_result;
87 // see stq_c
88 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
89 if (tmp == 1) {
90 xc->setStCondFailures(0);
91 }
92 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
93 0x2f: stq_c({{ Mem_uq = Ra; }},
94 {{
95 uint64_t tmp = write_result;
96 // If the write operation returns 0 or 1, then
97 // this was a conventional store conditional,
98 // and the value indicates the success/failure
99 // of the operation. If another value is
100 // returned, then this was a Turbolaser
101 // mailbox access, and we don't update the
102 // result register at all.
103 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
104 if (tmp == 1) {
105 // clear failure counter... this is
106 // non-architectural and for debugging
107 // only.
108 xc->setStCondFailures(0);
109 }
110 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
111 }
112
113 format IntegerOperate {
114
115 0x10: decode INTFUNC { // integer arithmetic operations
116
117 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
118 0x40: addlv({{
119 int32_t tmp = Ra_sl + Rb_or_imm_sl;
120 // signed overflow occurs when operands have same sign
121 // and sign of result does not match.
122 if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
123 fault = std::make_shared<IntegerOverflowFault>();
124 Rc_sl = tmp;
125 }});
126 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
127 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
128
129 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
130 0x60: addqv({{
131 uint64_t tmp = Ra + Rb_or_imm;
132 // signed overflow occurs when operands have same sign
133 // and sign of result does not match.
134 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
135 fault = std::make_shared<IntegerOverflowFault>();
136 Rc = tmp;
137 }});
138 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
139 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
140
141 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
142 0x49: sublv({{
143 int32_t tmp = Ra_sl - Rb_or_imm_sl;
144 // signed overflow detection is same as for add,
145 // except we need to look at the *complemented*
146 // sign bit of the subtrahend (Rb), i.e., if the initial
147 // signs are the *same* then no overflow can occur
148 if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
149 fault = std::make_shared<IntegerOverflowFault>();
150 Rc_sl = tmp;
151 }});
152 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
153 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
154
155 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
156 0x69: subqv({{
157 uint64_t tmp = Ra - Rb_or_imm;
158 // signed overflow detection is same as for add,
159 // except we need to look at the *complemented*
160 // sign bit of the subtrahend (Rb), i.e., if the initial
161 // signs are the *same* then no overflow can occur
162 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
163 fault = std::make_shared<IntegerOverflowFault>();
164 Rc = tmp;
165 }});
166 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
167 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
168
169 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
170 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
171 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
172 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
173 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
174
175 0x0f: cmpbge({{
176 int hi = 7;
177 int lo = 0;
178 uint64_t tmp = 0;
179 for (int i = 0; i < 8; ++i) {
180 tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
181 hi += 8;
182 lo += 8;
183 }
184 Rc = tmp;
185 }});
186 }
187
188 0x11: decode INTFUNC { // integer logical operations
189
190 0x00: and({{ Rc = Ra & Rb_or_imm; }});
191 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
192 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
193 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
194 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
195 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
196
197 // conditional moves
198 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
199 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
200 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
201 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
202 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
203 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
204 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
205 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
206
207 // For AMASK, RA must be R31.
208 0x61: decode RA {
209 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
210 }
211
212 // For IMPLVER, RA must be R31 and the B operand
213 // must be the immediate value 1.
214 0x6c: decode RA {
215 31: decode IMM {
216 1: decode INTIMM {
217 // return EV5 for FullSystem and EV6 otherwise
218 1: implver({{ Rc = FullSystem ? 1 : 2 }});
219 }
220 }
221 }
222
223 // The mysterious 11.25...
224 0x25: WarnUnimpl::eleven25();
225 }
226
227 0x12: decode INTFUNC {
228 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
229 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
230 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
231
232 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
233 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
234 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
235 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
236
237 0x52: mskwh({{
238 int bv = Rb_or_imm<2:0>;
239 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
240 }});
241 0x62: msklh({{
242 int bv = Rb_or_imm<2:0>;
243 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
244 }});
245 0x72: mskqh({{
246 int bv = Rb_or_imm<2:0>;
247 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
248 }});
249
250 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
251 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
252 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
253 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
254
255 0x5a: extwh({{
256 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
257 0x6a: extlh({{
258 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
259 0x7a: extqh({{
260 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
261
262 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
263 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
264 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
265 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
266
267 0x57: inswh({{
268 int bv = Rb_or_imm<2:0>;
269 Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
270 }});
271 0x67: inslh({{
272 int bv = Rb_or_imm<2:0>;
273 Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
274 }});
275 0x77: insqh({{
276 int bv = Rb_or_imm<2:0>;
277 Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
278 }});
279
280 0x30: zap({{
281 uint64_t zapmask = 0;
282 for (int i = 0; i < 8; ++i) {
283 if (Rb_or_imm<i:>)
284 zapmask |= (mask(8) << (i * 8));
285 }
286 Rc = Ra & ~zapmask;
287 }});
288 0x31: zapnot({{
289 uint64_t zapmask = 0;
290 for (int i = 0; i < 8; ++i) {
291 if (!Rb_or_imm<i:>)
292 zapmask |= (mask(8) << (i * 8));
293 }
294 Rc = Ra & ~zapmask;
295 }});
296 }
297
298 0x13: decode INTFUNC { // integer multiplies
299 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
300 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
301 0x30: umulh({{
302 uint64_t hi, lo;
303 mul128(Ra, Rb_or_imm, hi, lo);
304 Rc = hi;
305 }}, IntMultOp);
306 0x40: mullv({{
307 // 32-bit multiply with trap on overflow
308 int64_t Rax = Ra_sl; // sign extended version of Ra_sl
309 int64_t Rbx = Rb_or_imm_sl;
310 int64_t tmp = Rax * Rbx;
311 // To avoid overflow, all the upper 32 bits must match
312 // the sign bit of the lower 32. We code this as
313 // checking the upper 33 bits for all 0s or all 1s.
314 uint64_t sign_bits = tmp<63:31>;
315 if (sign_bits != 0 && sign_bits != mask(33))
316 fault = std::make_shared<IntegerOverflowFault>();
317 Rc_sl = tmp<31:0>;
318 }}, IntMultOp);
319 0x60: mulqv({{
320 // 64-bit multiply with trap on overflow
321 uint64_t hi, lo;
322 mul128(Ra, Rb_or_imm, hi, lo);
323 // all the upper 64 bits must match the sign bit of
324 // the lower 64
325 if (!((hi == 0 && lo<63:> == 0) ||
326 (hi == mask(64) && lo<63:> == 1)))
327 fault = std::make_shared<IntegerOverflowFault>();
328 Rc = lo;
329 }}, IntMultOp);
330 }
331
332 0x1c: decode INTFUNC {
333 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
334 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
335
336 0x30: ctpop({{
337 uint64_t count = 0;
338 for (int i = 0; Rb<63:i>; ++i) {
339 if (Rb<i:i> == 0x1)
340 ++count;
341 }
342 Rc = count;
343 }}, IntAluOp);
344
345 0x31: perr({{
346 uint64_t temp = 0;
347 int hi = 7;
348 int lo = 0;
349 for (int i = 0; i < 8; ++i) {
350 uint8_t ra_ub = Ra_uq<hi:lo>;
351 uint8_t rb_ub = Rb_uq<hi:lo>;
352 temp += (ra_ub >= rb_ub) ?
353 (ra_ub - rb_ub) : (rb_ub - ra_ub);
354 hi += 8;
355 lo += 8;
356 }
357 Rc = temp;
358 }});
359
360 0x32: ctlz({{
361 uint64_t count = 0;
362 uint64_t temp = Rb;
363 if (temp<63:32>) temp >>= 32; else count += 32;
364 if (temp<31:16>) temp >>= 16; else count += 16;
365 if (temp<15:8>) temp >>= 8; else count += 8;
366 if (temp<7:4>) temp >>= 4; else count += 4;
367 if (temp<3:2>) temp >>= 2; else count += 2;
368 if (temp<1:1>) temp >>= 1; else count += 1;
369 if ((temp<0:0>) != 0x1) count += 1;
370 Rc = count;
371 }}, IntAluOp);
372
373 0x33: cttz({{
374 uint64_t count = 0;
375 uint64_t temp = Rb;
376 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
377 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
378 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
379 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
380 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
381 if (!(temp<0:0> & ULL(0x1))) {
382 temp >>= 1; count += 1;
383 }
384 if (!(temp<0:0> & ULL(0x1))) count += 1;
385 Rc = count;
386 }}, IntAluOp);
387
388
389 0x34: unpkbw({{
390 Rc = (Rb_uq<7:0>
391 | (Rb_uq<15:8> << 16)
392 | (Rb_uq<23:16> << 32)
393 | (Rb_uq<31:24> << 48));
394 }}, IntAluOp);
395
396 0x35: unpkbl({{
397 Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
398 }}, IntAluOp);
399
400 0x36: pkwb({{
401 Rc = (Rb_uq<7:0>
402 | (Rb_uq<23:16> << 8)
403 | (Rb_uq<39:32> << 16)
404 | (Rb_uq<55:48> << 24));
405 }}, IntAluOp);
406
407 0x37: pklb({{
408 Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
409 }}, IntAluOp);
410
411 0x38: minsb8({{
412 uint64_t temp = 0;
413 int hi = 63;
414 int lo = 56;
415 for (int i = 7; i >= 0; --i) {
416 int8_t ra_sb = Ra_uq<hi:lo>;
417 int8_t rb_sb = Rb_uq<hi:lo>;
418 temp = ((temp << 8)
419 | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
420 : Rb_uq<hi:lo>));
421 hi -= 8;
422 lo -= 8;
423 }
424 Rc = temp;
425 }});
426
427 0x39: minsw4({{
428 uint64_t temp = 0;
429 int hi = 63;
430 int lo = 48;
431 for (int i = 3; i >= 0; --i) {
432 int16_t ra_sw = Ra_uq<hi:lo>;
433 int16_t rb_sw = Rb_uq<hi:lo>;
434 temp = ((temp << 16)
435 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
436 : Rb_uq<hi:lo>));
437 hi -= 16;
438 lo -= 16;
439 }
440 Rc = temp;
441 }});
442
443 0x3a: minub8({{
444 uint64_t temp = 0;
445 int hi = 63;
446 int lo = 56;
447 for (int i = 7; i >= 0; --i) {
448 uint8_t ra_ub = Ra_uq<hi:lo>;
449 uint8_t rb_ub = Rb_uq<hi:lo>;
450 temp = ((temp << 8)
451 | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
452 : Rb_uq<hi:lo>));
453 hi -= 8;
454 lo -= 8;
455 }
456 Rc = temp;
457 }});
458
459 0x3b: minuw4({{
460 uint64_t temp = 0;
461 int hi = 63;
462 int lo = 48;
463 for (int i = 3; i >= 0; --i) {
464 uint16_t ra_sw = Ra_uq<hi:lo>;
465 uint16_t rb_sw = Rb_uq<hi:lo>;
466 temp = ((temp << 16)
467 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
468 : Rb_uq<hi:lo>));
469 hi -= 16;
470 lo -= 16;
471 }
472 Rc = temp;
473 }});
474
475 0x3c: maxub8({{
476 uint64_t temp = 0;
477 int hi = 63;
478 int lo = 56;
479 for (int i = 7; i >= 0; --i) {
480 uint8_t ra_ub = Ra_uq<hi:lo>;
481 uint8_t rb_ub = Rb_uq<hi:lo>;
482 temp = ((temp << 8)
483 | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
484 : Rb_uq<hi:lo>));
485 hi -= 8;
486 lo -= 8;
487 }
488 Rc = temp;
489 }});
490
491 0x3d: maxuw4({{
492 uint64_t temp = 0;
493 int hi = 63;
494 int lo = 48;
495 for (int i = 3; i >= 0; --i) {
496 uint16_t ra_uw = Ra_uq<hi:lo>;
497 uint16_t rb_uw = Rb_uq<hi:lo>;
498 temp = ((temp << 16)
499 | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
500 : Rb_uq<hi:lo>));
501 hi -= 16;
502 lo -= 16;
503 }
504 Rc = temp;
505 }});
506
507 0x3e: maxsb8({{
508 uint64_t temp = 0;
509 int hi = 63;
510 int lo = 56;
511 for (int i = 7; i >= 0; --i) {
512 int8_t ra_sb = Ra_uq<hi:lo>;
513 int8_t rb_sb = Rb_uq<hi:lo>;
514 temp = ((temp << 8)
515 | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
516 : Rb_uq<hi:lo>));
517 hi -= 8;
518 lo -= 8;
519 }
520 Rc = temp;
521 }});
522
523 0x3f: maxsw4({{
524 uint64_t temp = 0;
525 int hi = 63;
526 int lo = 48;
527 for (int i = 3; i >= 0; --i) {
528 int16_t ra_sw = Ra_uq<hi:lo>;
529 int16_t rb_sw = Rb_uq<hi:lo>;
530 temp = ((temp << 16)
531 | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
532 : Rb_uq<hi:lo>));
533 hi -= 16;
534 lo -= 16;
535 }
536 Rc = temp;
537 }});
538
539 format BasicOperateWithNopCheck {
540 0x70: decode RB {
541 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
542 }
543 0x78: decode RB {
544 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
545 FloatCvtOp);
546 }
547 }
548 }
549 }
550
551 // Conditional branches.
552 format CondBranch {
553 0x39: beq({{ cond = (Ra == 0); }});
554 0x3d: bne({{ cond = (Ra != 0); }});
555 0x3e: bge({{ cond = (Ra_sq >= 0); }});
556 0x3f: bgt({{ cond = (Ra_sq > 0); }});
557 0x3b: ble({{ cond = (Ra_sq <= 0); }});
558 0x3a: blt({{ cond = (Ra_sq < 0); }});
559 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
560 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
561
562 0x31: fbeq({{ cond = (Fa == 0); }});
563 0x35: fbne({{ cond = (Fa != 0); }});
564 0x36: fbge({{ cond = (Fa >= 0); }});
565 0x37: fbgt({{ cond = (Fa > 0); }});
566 0x33: fble({{ cond = (Fa <= 0); }});
567 0x32: fblt({{ cond = (Fa < 0); }});
568 }
569
570 // unconditional branches
571 format UncondBranch {
572 0x30: br();
573 0x34: bsr(IsCall);
574 }
575
576 // indirect branches
577 0x1a: decode JMPFUNC {
578 format Jump {
579 0: jmp();
580 1: jsr(IsCall);
581 2: ret(IsReturn);
582 3: jsr_coroutine(IsCall, IsReturn);
583 }
584 }
585
586 // Square root and integer-to-FP moves
587 0x14: decode FP_SHORTFUNC {
588 // Integer to FP register moves must have RB == 31
589 0x4: decode RB {
590 31: decode FP_FULLFUNC {
591 format BasicOperateWithNopCheck {
592 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
593 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
594 0x014: FailUnimpl::itoff(); // VAX-format conversion
595 }
596 }
597 }
598
599 // Square root instructions must have FA == 31
600 0xb: decode FA {
601 31: decode FP_TYPEFUNC {
602 format FloatingPointOperate {
603 0x0b: sqrts({{
604 if (Fb_sf < 0.0)
605 fault = std::make_shared<ArithmeticFault>();
606 Fc_sf = sqrt(Fb_sf);
607 }}, FloatSqrtOp);
608 0x2b: sqrtt({{
609 if (Fb < 0.0)
610 fault = std::make_shared<ArithmeticFault>();
611 Fc = sqrt(Fb);
612 }}, FloatSqrtOp);
613 }
614 }
615 }
616
617 // VAX-format sqrtf and sqrtg are not implemented
618 0xa: FailUnimpl::sqrtfg();
619 }
620
621 // IEEE floating point
622 0x16: decode FP_SHORTFUNC_TOP2 {
623 // The top two bits of the short function code break this
624 // space into four groups: binary ops, compares, reserved, and
625 // conversions. See Table 4-12 of AHB. There are different
626 // special cases in these different groups, so we decode on
627 // these top two bits first just to select a decode strategy.
628 // Most of these instructions may have various trapping and
629 // rounding mode flags set; these are decoded in the
630 // FloatingPointDecode template used by the
631 // FloatingPointOperate format.
632
633 // add/sub/mul/div: just decode on the short function code
634 // and source type. All valid trapping and rounding modes apply.
635 0: decode FP_TRAPMODE {
636 // check for valid trapping modes here
637 0,1,5,7: decode FP_TYPEFUNC {
638 format FloatingPointOperate {
639 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
640 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
641 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
642 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
643
644 0x20: addt({{ Fc = Fa + Fb; }});
645 0x21: subt({{ Fc = Fa - Fb; }});
646 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
647 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
648 }
649 }
650 }
651
652 // Floating-point compare instructions must have the default
653 // rounding mode, and may use the default trapping mode or
654 // /SU. Both trapping modes are treated the same by M5; the
655 // only difference on the real hardware (as far a I can tell)
656 // is that without /SU you'd get an imprecise trap if you
657 // tried to compare a NaN with something else (instead of an
658 // "unordered" result).
659 1: decode FP_FULLFUNC {
660 format BasicOperateWithNopCheck {
661 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
662 FloatCmpOp);
663 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
664 FloatCmpOp);
665 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
666 FloatCmpOp);
667 0x0a4, 0x5a4: cmptun({{ // unordered
668 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
669 }}, FloatCmpOp);
670 }
671 }
672
673 // The FP-to-integer and integer-to-FP conversion insts
674 // require that FA be 31.
675 3: decode FA {
676 31: decode FP_TYPEFUNC {
677 format FloatingPointOperate {
678 0x2f: decode FP_ROUNDMODE {
679 format FPFixedRounding {
680 // "chopped" i.e. round toward zero
681 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
682 Chopped);
683 // round to minus infinity
684 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
685 MinusInfinity);
686 }
687 default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
688 }
689
690 // The cvtts opcode is overloaded to be cvtst if the trap
691 // mode is 2 or 6 (which are not valid otherwise)
692 0x2c: decode FP_FULLFUNC {
693 format BasicOperateWithNopCheck {
694 // trap on denorm version "cvtst/s" is
695 // simulated same as cvtst
696 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
697 }
698 default: cvtts({{ Fc_sf = Fb; }});
699 }
700
701 // The trapping mode for integer-to-FP conversions
702 // must be /SUI or nothing; /U and /SU are not
703 // allowed. The full set of rounding modes are
704 // supported though.
705 0x3c: decode FP_TRAPMODE {
706 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
707 }
708 0x3e: decode FP_TRAPMODE {
709 0,7: cvtqt({{ Fc = Fb_sq; }});
710 }
711 }
712 }
713 }
714 }
715
716 // misc FP operate
717 0x17: decode FP_FULLFUNC {
718 format BasicOperateWithNopCheck {
719 0x010: cvtlq({{
720 Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
721 }});
722 0x030: cvtql({{
723 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
724 }});
725
726 // We treat the precise & imprecise trapping versions of
727 // cvtql identically.
728 0x130, 0x530: cvtqlv({{
729 // To avoid overflow, all the upper 32 bits must match
730 // the sign bit of the lower 32. We code this as
731 // checking the upper 33 bits for all 0s or all 1s.
732 uint64_t sign_bits = Fb_uq<63:31>;
733 if (sign_bits != 0 && sign_bits != mask(33))
734 fault = std::make_shared<IntegerOverflowFault>();
735 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
736 }});
737
738 0x020: cpys({{ // copy sign
739 Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
740 }});
741 0x021: cpysn({{ // copy sign negated
742 Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
743 }});
744 0x022: cpyse({{ // copy sign and exponent
745 Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
746 }});
747
748 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
749 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
750 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
751 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
752 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
753 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
754
755 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
756 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
757 }
758 }
759
760 // miscellaneous mem-format ops
761 0x18: decode MEMFUNC {
762 format WarnUnimpl {
763 0x8000: fetch();
764 0xa000: fetch_m();
765 0xe800: ecb();
766 }
767
768 format MiscPrefetch {
769 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
770 {{ ; }},
771 mem_flags = PREFETCH);
772 }
773
774 format BasicOperate {
775 0xc000: rpcc({{
776 /* Rb is a fake dependency so here is a fun way to get
777 * the parser to understand that.
778 */
779 uint64_t unused_var M5_VAR_USED = Rb;
780 Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
781 }}, IsUnverifiable);
782
783 // All of the barrier instructions below do nothing in
784 // their execute() methods (hence the empty code blocks).
785 // All of their functionality is hard-coded in the
786 // pipeline based on the flags IsSerializing,
787 // IsMemBarrier, and IsWriteBarrier. In the current
788 // detailed CPU model, the execute() function only gets
789 // called at fetch, so there's no way to generate pipeline
790 // behavior at any other stage. Once we go to an
791 // exec-in-exec CPU model we should be able to get rid of
792 // these flags and implement this behavior via the
793 // execute() methods.
794
795 // trapb is just a barrier on integer traps, where excb is
796 // a barrier on integer and FP traps. "EXCB is thus a
797 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
798 // them the same though.
799 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
800 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
801 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
802 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
803 }
804
805 0xe000: decode FullSystemInt {
806 0: FailUnimpl::rc_se();
807 default: BasicOperate::rc({{
808 Ra = IntrFlag;
809 IntrFlag = 0;
810 }}, IsNonSpeculative, IsUnverifiable);
811 }
812 0xf000: decode FullSystemInt {
813 0: FailUnimpl::rs_se();
814 default: BasicOperate::rs({{
815 Ra = IntrFlag;
816 IntrFlag = 1;
817 }}, IsNonSpeculative, IsUnverifiable);
818 }
819 }
820
821 0x00: decode FullSystemInt {
822 0: decode PALFUNC {
823 format EmulatedCallPal {
824 0x00: halt ({{
825 exitSimLoop("halt instruction encountered");
826 }}, IsNonSpeculative);
827 0x83: callsys({{
828 xc->syscall(&fault);
829 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
830 // Read uniq reg into ABI return value register (r0)
831 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
832 // Write uniq reg with value from ABI arg register (r16)
833 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
834 }
835 }
836 default: CallPal::call_pal({{
837 if (!palValid ||
838 (palPriv
839 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
840 // invalid pal function code, or attempt to do privileged
841 // PAL call in non-kernel mode
842 fault = std::make_shared<UnimplementedOpcodeFault>();
843 } else {
844 // check to see if simulator wants to do something special
845 // on this PAL call (including maybe suppress it)
846 bool dopal = true;
847 ThreadContext *tc = xc->tcBase();
848 auto *base_stats = tc->getKernelStats();
849 auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
850 base_stats);
851 assert(stats || !base_stats);
852 if (stats)
853 stats->callpal(palFunc, tc);
854
855 System *sys = tc->getSystemPtr();
856
857 switch (palFunc) {
858 case PAL::halt:
859 xc->tcBase()->halt();
860 if (--System::numSystemsRunning == 0)
861 exitSimLoop("all cpus halted");
862 break;
863
864 case PAL::bpt:
865 case PAL::bugchk:
866 if (sys->breakpoint())
867 dopal = false;
868 break;
869 }
870
871 if (dopal) {
872 xc->setMiscReg(IPR_EXC_ADDR, NPC);
873 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
874 }
875 }
876 }}, IsNonSpeculative);
877 }
878
879 0x1b: decode PALMODE {
880 0: OpcdecFault::hw_st_quad();
881 1: decode HW_LDST_QUAD {
882 format HwLoad {
883 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
884 L, IsSerializing, IsSerializeBefore);
885 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
886 Q, IsSerializing, IsSerializeBefore);
887 }
888 }
889 }
890
891 0x1f: decode PALMODE {
892 0: OpcdecFault::hw_st_cond();
893 format HwStore {
894 1: decode HW_LDST_COND {
895 0: decode HW_LDST_QUAD {
896 0: hw_st({{ EA = (Rb + disp) & ~3; }},
897 {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
898 1: hw_st({{ EA = (Rb + disp) & ~7; }},
899 {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
900 }
901
902 1: FailUnimpl::hw_st_cond();
903 }
904 }
905 }
906
907 0x19: decode PALMODE {
908 0: OpcdecFault::hw_mfpr();
909 format HwMoveIPR {
910 1: hw_mfpr({{
911 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
912 IprToMiscRegIndex[ipr_index] : -1;
913 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
914 miscRegIndex >= NumInternalProcRegs)
915 fault = std::make_shared<UnimplementedOpcodeFault>();
916 else
917 Ra = xc->readMiscReg(miscRegIndex);
918 }}, IsIprAccess);
919 }
920 }
921
922 0x1d: decode PALMODE {
923 0: OpcdecFault::hw_mtpr();
924 format HwMoveIPR {
925 1: hw_mtpr({{
926 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
927 IprToMiscRegIndex[ipr_index] : -1;
928 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
929 miscRegIndex >= NumInternalProcRegs)
930 fault = std::make_shared<UnimplementedOpcodeFault>();
931 else
932 xc->setMiscReg(miscRegIndex, Ra);
933 if (traceData) { traceData->setData(Ra); }
934 }}, IsIprAccess);
935 }
936 }
937
938 0x1e: decode PALMODE {
939 0: OpcdecFault::hw_rei();
940 format BasicOperate {
941 1: hw_rei({{
942 Addr pc = PC;
943 if (!(pc & 0x3))
944 return std::make_shared<UnimplementedOpcodeFault>();
945
946 LockFlag = false;
947 NPC = IprExcAddr;
948
949 ThreadContext *tc = xc->tcBase();
950 auto *base_stats = tc->getKernelStats();
951 auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
952 base_stats);
953 assert(stats || !base_stats);
954 if (stats)
955 stats->hwrei();
956
957 CPA::cpa()->swAutoBegin(tc, IprExcAddr);
958 }}, IsSerializing, IsSerializeBefore);
959 }
960 }
961
962 format BasicOperate {
963 // M5 special opcodes use the reserved 0x01 opcode space
964 0x01: decode M5FUNC {
965 0x00: arm({{
966 PseudoInst::arm(xc->tcBase());
967 }}, IsNonSpeculative);
968 0x01: quiesce({{
969 // Don't sleep if (unmasked) interrupts are pending
970 BaseInterrupts* interrupts =
971 xc->tcBase()->getCpuPtr()->getInterruptController(0);
972 if (interrupts->checkInterrupts(xc->tcBase())) {
973 PseudoInst::quiesceSkip(xc->tcBase());
974 } else {
975 PseudoInst::quiesce(xc->tcBase());
976 }
977 }}, IsNonSpeculative, IsQuiesce);
978 0x02: quiesceNs({{
979 PseudoInst::quiesceNs(xc->tcBase(), R16);
980 }}, IsNonSpeculative, IsQuiesce);
981 0x03: quiesceCycles({{
982 PseudoInst::quiesceCycles(xc->tcBase(), R16);
983 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
984 0x04: quiesceTime({{
985 R0 = PseudoInst::quiesceTime(xc->tcBase());
986 }}, IsNonSpeculative, IsUnverifiable);
987 0x07: rpns({{
988 R0 = PseudoInst::rpns(xc->tcBase());
989 }}, IsNonSpeculative, IsUnverifiable);
990 0x09: wakeCPU({{
991 PseudoInst::wakeCPU(xc->tcBase(), R16);
992 }}, IsNonSpeculative, IsUnverifiable);
993 0x10: deprecated_ivlb({{
994 warn_once("Obsolete M5 ivlb instruction encountered.\n");
995 }});
996 0x11: deprecated_ivle({{
997 warn_once("Obsolete M5 ivlb instruction encountered.\n");
998 }});
999 0x20: deprecated_exit ({{
1000 warn_once("deprecated M5 exit instruction encountered.\n");
1001 PseudoInst::m5exit(xc->tcBase(), 0);
1002 }}, No_OpClass, IsNonSpeculative);
1003 0x21: m5exit({{
1004 PseudoInst::m5exit(xc->tcBase(), R16);
1005 }}, No_OpClass, IsNonSpeculative);
1006 0x31: loadsymbol({{
1007 PseudoInst::loadsymbol(xc->tcBase());
1008 }}, No_OpClass, IsNonSpeculative);
1009 0x30: initparam({{
1010 Ra = PseudoInst::initParam(xc->tcBase(), R16, R17);
1011 }});
1012 0x40: resetstats({{
1013 PseudoInst::resetstats(xc->tcBase(), R16, R17);
1014 }}, IsNonSpeculative);
1015 0x41: dumpstats({{
1016 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
1017 }}, IsNonSpeculative);
1018 0x42: dumpresetstats({{
1019 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
1020 }}, IsNonSpeculative);
1021 0x43: m5checkpoint({{
1022 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
1023 }}, IsNonSpeculative);
1024 0x50: m5readfile({{
1025 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
1026 }}, IsNonSpeculative);
1027 0x51: m5break({{
1028 PseudoInst::debugbreak(xc->tcBase());
1029 }}, IsNonSpeculative);
1030 0x52: m5switchcpu({{
1031 PseudoInst::switchcpu(xc->tcBase());
1032 }}, IsNonSpeculative);
1033 0x53: m5addsymbol({{
1034 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
1035 }}, IsNonSpeculative);
1036 0x54: m5panic({{
1037 panic("M5 panic instruction called at pc = %#x.", PC);
1038 }}, IsNonSpeculative);
1039 #define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
1040 0x55: decode RA {
1041 0x00: m5a_old({{
1042 panic("Deprecated M5 annotate instruction executed "
1043 "at pc = %#x\n", PC);
1044 }}, IsNonSpeculative);
1045 0x01: m5a_bsm({{
1046 CPANN(swSmBegin);
1047 }}, IsNonSpeculative);
1048 0x02: m5a_esm({{
1049 CPANN(swSmEnd);
1050 }}, IsNonSpeculative);
1051 0x03: m5a_begin({{
1052 CPANN(swExplictBegin);
1053 }}, IsNonSpeculative);
1054 0x04: m5a_end({{
1055 CPANN(swEnd);
1056 }}, IsNonSpeculative);
1057 0x06: m5a_q({{
1058 CPANN(swQ);
1059 }}, IsNonSpeculative);
1060 0x07: m5a_dq({{
1061 CPANN(swDq);
1062 }}, IsNonSpeculative);
1063 0x08: m5a_wf({{
1064 CPANN(swWf);
1065 }}, IsNonSpeculative);
1066 0x09: m5a_we({{
1067 CPANN(swWe);
1068 }}, IsNonSpeculative);
1069 0x0C: m5a_sq({{
1070 CPANN(swSq);
1071 }}, IsNonSpeculative);
1072 0x0D: m5a_aq({{
1073 CPANN(swAq);
1074 }}, IsNonSpeculative);
1075 0x0E: m5a_pq({{
1076 CPANN(swPq);
1077 }}, IsNonSpeculative);
1078 0x0F: m5a_l({{
1079 CPANN(swLink);
1080 }}, IsNonSpeculative);
1081 0x10: m5a_identify({{
1082 CPANN(swIdentify);
1083 }}, IsNonSpeculative);
1084 0x11: m5a_getid({{
1085 R0 = CPANN(swGetId);
1086 }}, IsNonSpeculative);
1087 0x13: m5a_scl({{
1088 CPANN(swSyscallLink);
1089 }}, IsNonSpeculative);
1090 0x14: m5a_rq({{
1091 CPANN(swRq);
1092 }}, IsNonSpeculative);
1093 } // M5 Annotate Operations
1094 #undef CPANN
1095 0x56: m5reserved2({{
1096 warn("M5 reserved opcode ignored");
1097 }}, IsNonSpeculative);
1098 0x57: m5reserved3({{
1099 warn("M5 reserved opcode ignored");
1100 }}, IsNonSpeculative);
1101 0x58: m5reserved4({{
1102 warn("M5 reserved opcode ignored");
1103 }}, IsNonSpeculative);
1104 0x59: m5reserved5({{
1105 warn("M5 reserved opcode ignored");
1106 }}, IsNonSpeculative);
1107 }
1108 }
1109 }