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[gem5.git] / src / arch / alpha / isa / decoder.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2003-2006 The Regents of The University of Michigan
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 //
29 // Authors: Steve Reinhardt
30
31 ////////////////////////////////////////////////////////////////////
32 //
33 // The actual decoder specification
34 //
35
36 decode OPCODE default Unknown::unknown() {
37
38 format LoadAddress {
39 0x08: lda({{ Ra = Rb + disp; }});
40 0x09: ldah({{ Ra = Rb + (disp << 16); }});
41 }
42
43 format LoadOrNop {
44 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47 0x23: ldt({{ Fa = Mem.df; }});
48 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
49 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
50 }
51
52 format LoadOrPrefetch {
53 0x28: ldl({{ Ra.sl = Mem.sl; }});
54 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
55 // IsFloating flag on lds gets the prefetch to disassemble
56 // using f31 instead of r31... funcitonally it's unnecessary
57 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
58 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
59 }
60
61 format Store {
62 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
63 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
64 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
65 0x2d: stq({{ Mem.uq = Ra.uq; }});
66 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
67 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
68 0x27: stt({{ Mem.df = Fa; }});
69 }
70
71 format StoreCond {
72 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
73 {{
74 uint64_t tmp = write_result;
75 // see stq_c
76 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
77 if (tmp == 1) {
78 xc->setStCondFailures(0);
79 }
80 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
81 0x2f: stq_c({{ Mem.uq = Ra; }},
82 {{
83 uint64_t tmp = write_result;
84 // If the write operation returns 0 or 1, then
85 // this was a conventional store conditional,
86 // and the value indicates the success/failure
87 // of the operation. If another value is
88 // returned, then this was a Turbolaser
89 // mailbox access, and we don't update the
90 // result register at all.
91 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
92 if (tmp == 1) {
93 // clear failure counter... this is
94 // non-architectural and for debugging
95 // only.
96 xc->setStCondFailures(0);
97 }
98 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
99 }
100
101 format IntegerOperate {
102
103 0x10: decode INTFUNC { // integer arithmetic operations
104
105 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
106 0x40: addlv({{
107 int32_t tmp = Ra.sl + Rb_or_imm.sl;
108 // signed overflow occurs when operands have same sign
109 // and sign of result does not match.
110 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
111 fault = new IntegerOverflowFault;
112 Rc.sl = tmp;
113 }});
114 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
115 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
116
117 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
118 0x60: addqv({{
119 uint64_t tmp = Ra + Rb_or_imm;
120 // signed overflow occurs when operands have same sign
121 // and sign of result does not match.
122 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
123 fault = new IntegerOverflowFault;
124 Rc = tmp;
125 }});
126 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
127 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
128
129 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
130 0x49: sublv({{
131 int32_t tmp = Ra.sl - Rb_or_imm.sl;
132 // signed overflow detection is same as for add,
133 // except we need to look at the *complemented*
134 // sign bit of the subtrahend (Rb), i.e., if the initial
135 // signs are the *same* then no overflow can occur
136 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
137 fault = new IntegerOverflowFault;
138 Rc.sl = tmp;
139 }});
140 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
141 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
142
143 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
144 0x69: subqv({{
145 uint64_t tmp = Ra - Rb_or_imm;
146 // signed overflow detection is same as for add,
147 // except we need to look at the *complemented*
148 // sign bit of the subtrahend (Rb), i.e., if the initial
149 // signs are the *same* then no overflow can occur
150 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
151 fault = new IntegerOverflowFault;
152 Rc = tmp;
153 }});
154 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
155 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
156
157 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
158 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
159 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
160 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
161 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
162
163 0x0f: cmpbge({{
164 int hi = 7;
165 int lo = 0;
166 uint64_t tmp = 0;
167 for (int i = 0; i < 8; ++i) {
168 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
169 hi += 8;
170 lo += 8;
171 }
172 Rc = tmp;
173 }});
174 }
175
176 0x11: decode INTFUNC { // integer logical operations
177
178 0x00: and({{ Rc = Ra & Rb_or_imm; }});
179 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
180 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
181 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
182 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
183 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
184
185 // conditional moves
186 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
187 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
188 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
189 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
190 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
191 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
192 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
193 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
194
195 // For AMASK, RA must be R31.
196 0x61: decode RA {
197 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
198 }
199
200 // For IMPLVER, RA must be R31 and the B operand
201 // must be the immediate value 1.
202 0x6c: decode RA {
203 31: decode IMM {
204 1: decode INTIMM {
205 // return EV5 for FULL_SYSTEM and EV6 otherwise
206 1: implver({{
207 #if FULL_SYSTEM
208 Rc = 1;
209 #else
210 Rc = 2;
211 #endif
212 }});
213 }
214 }
215 }
216
217 #if FULL_SYSTEM
218 // The mysterious 11.25...
219 0x25: WarnUnimpl::eleven25();
220 #endif
221 }
222
223 0x12: decode INTFUNC {
224 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
225 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
226 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
227
228 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
229 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
230 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
231 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
232
233 0x52: mskwh({{
234 int bv = Rb_or_imm<2:0>;
235 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
236 }});
237 0x62: msklh({{
238 int bv = Rb_or_imm<2:0>;
239 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
240 }});
241 0x72: mskqh({{
242 int bv = Rb_or_imm<2:0>;
243 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
244 }});
245
246 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
247 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
248 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
249 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
250
251 0x5a: extwh({{
252 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
253 0x6a: extlh({{
254 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
255 0x7a: extqh({{
256 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
257
258 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
259 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
260 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
261 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
262
263 0x57: inswh({{
264 int bv = Rb_or_imm<2:0>;
265 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
266 }});
267 0x67: inslh({{
268 int bv = Rb_or_imm<2:0>;
269 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
270 }});
271 0x77: insqh({{
272 int bv = Rb_or_imm<2:0>;
273 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
274 }});
275
276 0x30: zap({{
277 uint64_t zapmask = 0;
278 for (int i = 0; i < 8; ++i) {
279 if (Rb_or_imm<i:>)
280 zapmask |= (mask(8) << (i * 8));
281 }
282 Rc = Ra & ~zapmask;
283 }});
284 0x31: zapnot({{
285 uint64_t zapmask = 0;
286 for (int i = 0; i < 8; ++i) {
287 if (!Rb_or_imm<i:>)
288 zapmask |= (mask(8) << (i * 8));
289 }
290 Rc = Ra & ~zapmask;
291 }});
292 }
293
294 0x13: decode INTFUNC { // integer multiplies
295 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
296 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
297 0x30: umulh({{
298 uint64_t hi, lo;
299 mul128(Ra, Rb_or_imm, hi, lo);
300 Rc = hi;
301 }}, IntMultOp);
302 0x40: mullv({{
303 // 32-bit multiply with trap on overflow
304 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
305 int64_t Rbx = Rb_or_imm.sl;
306 int64_t tmp = Rax * Rbx;
307 // To avoid overflow, all the upper 32 bits must match
308 // the sign bit of the lower 32. We code this as
309 // checking the upper 33 bits for all 0s or all 1s.
310 uint64_t sign_bits = tmp<63:31>;
311 if (sign_bits != 0 && sign_bits != mask(33))
312 fault = new IntegerOverflowFault;
313 Rc.sl = tmp<31:0>;
314 }}, IntMultOp);
315 0x60: mulqv({{
316 // 64-bit multiply with trap on overflow
317 uint64_t hi, lo;
318 mul128(Ra, Rb_or_imm, hi, lo);
319 // all the upper 64 bits must match the sign bit of
320 // the lower 64
321 if (!((hi == 0 && lo<63:> == 0) ||
322 (hi == mask(64) && lo<63:> == 1)))
323 fault = new IntegerOverflowFault;
324 Rc = lo;
325 }}, IntMultOp);
326 }
327
328 0x1c: decode INTFUNC {
329 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
330 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
331
332 0x30: ctpop({{
333 uint64_t count = 0;
334 for (int i = 0; Rb<63:i>; ++i) {
335 if (Rb<i:i> == 0x1)
336 ++count;
337 }
338 Rc = count;
339 }}, IntAluOp);
340
341 0x31: perr({{
342 uint64_t temp = 0;
343 int hi = 7;
344 int lo = 0;
345 for (int i = 0; i < 8; ++i) {
346 uint8_t ra_ub = Ra.uq<hi:lo>;
347 uint8_t rb_ub = Rb.uq<hi:lo>;
348 temp += (ra_ub >= rb_ub) ?
349 (ra_ub - rb_ub) : (rb_ub - ra_ub);
350 hi += 8;
351 lo += 8;
352 }
353 Rc = temp;
354 }});
355
356 0x32: ctlz({{
357 uint64_t count = 0;
358 uint64_t temp = Rb;
359 if (temp<63:32>) temp >>= 32; else count += 32;
360 if (temp<31:16>) temp >>= 16; else count += 16;
361 if (temp<15:8>) temp >>= 8; else count += 8;
362 if (temp<7:4>) temp >>= 4; else count += 4;
363 if (temp<3:2>) temp >>= 2; else count += 2;
364 if (temp<1:1>) temp >>= 1; else count += 1;
365 if ((temp<0:0>) != 0x1) count += 1;
366 Rc = count;
367 }}, IntAluOp);
368
369 0x33: cttz({{
370 uint64_t count = 0;
371 uint64_t temp = Rb;
372 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
373 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
374 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
375 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
376 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
377 if (!(temp<0:0> & ULL(0x1))) {
378 temp >>= 1; count += 1;
379 }
380 if (!(temp<0:0> & ULL(0x1))) count += 1;
381 Rc = count;
382 }}, IntAluOp);
383
384
385 0x34: unpkbw({{
386 Rc = (Rb.uq<7:0>
387 | (Rb.uq<15:8> << 16)
388 | (Rb.uq<23:16> << 32)
389 | (Rb.uq<31:24> << 48));
390 }}, IntAluOp);
391
392 0x35: unpkbl({{
393 Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32));
394 }}, IntAluOp);
395
396 0x36: pkwb({{
397 Rc = (Rb.uq<7:0>
398 | (Rb.uq<23:16> << 8)
399 | (Rb.uq<39:32> << 16)
400 | (Rb.uq<55:48> << 24));
401 }}, IntAluOp);
402
403 0x37: pklb({{
404 Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8));
405 }}, IntAluOp);
406
407 0x38: minsb8({{
408 uint64_t temp = 0;
409 int hi = 63;
410 int lo = 56;
411 for (int i = 7; i >= 0; --i) {
412 int8_t ra_sb = Ra.uq<hi:lo>;
413 int8_t rb_sb = Rb.uq<hi:lo>;
414 temp = ((temp << 8)
415 | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
416 : Rb.uq<hi:lo>));
417 hi -= 8;
418 lo -= 8;
419 }
420 Rc = temp;
421 }});
422
423 0x39: minsw4({{
424 uint64_t temp = 0;
425 int hi = 63;
426 int lo = 48;
427 for (int i = 3; i >= 0; --i) {
428 int16_t ra_sw = Ra.uq<hi:lo>;
429 int16_t rb_sw = Rb.uq<hi:lo>;
430 temp = ((temp << 16)
431 | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
432 : Rb.uq<hi:lo>));
433 hi -= 16;
434 lo -= 16;
435 }
436 Rc = temp;
437 }});
438
439 0x3a: minub8({{
440 uint64_t temp = 0;
441 int hi = 63;
442 int lo = 56;
443 for (int i = 7; i >= 0; --i) {
444 uint8_t ra_ub = Ra.uq<hi:lo>;
445 uint8_t rb_ub = Rb.uq<hi:lo>;
446 temp = ((temp << 8)
447 | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
448 : Rb.uq<hi:lo>));
449 hi -= 8;
450 lo -= 8;
451 }
452 Rc = temp;
453 }});
454
455 0x3b: minuw4({{
456 uint64_t temp = 0;
457 int hi = 63;
458 int lo = 48;
459 for (int i = 3; i >= 0; --i) {
460 uint16_t ra_sw = Ra.uq<hi:lo>;
461 uint16_t rb_sw = Rb.uq<hi:lo>;
462 temp = ((temp << 16)
463 | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
464 : Rb.uq<hi:lo>));
465 hi -= 16;
466 lo -= 16;
467 }
468 Rc = temp;
469 }});
470
471 0x3c: maxub8({{
472 uint64_t temp = 0;
473 int hi = 63;
474 int lo = 56;
475 for (int i = 7; i >= 0; --i) {
476 uint8_t ra_ub = Ra.uq<hi:lo>;
477 uint8_t rb_ub = Rb.uq<hi:lo>;
478 temp = ((temp << 8)
479 | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
480 : Rb.uq<hi:lo>));
481 hi -= 8;
482 lo -= 8;
483 }
484 Rc = temp;
485 }});
486
487 0x3d: maxuw4({{
488 uint64_t temp = 0;
489 int hi = 63;
490 int lo = 48;
491 for (int i = 3; i >= 0; --i) {
492 uint16_t ra_uw = Ra.uq<hi:lo>;
493 uint16_t rb_uw = Rb.uq<hi:lo>;
494 temp = ((temp << 16)
495 | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
496 : Rb.uq<hi:lo>));
497 hi -= 16;
498 lo -= 16;
499 }
500 Rc = temp;
501 }});
502
503 0x3e: maxsb8({{
504 uint64_t temp = 0;
505 int hi = 63;
506 int lo = 56;
507 for (int i = 7; i >= 0; --i) {
508 int8_t ra_sb = Ra.uq<hi:lo>;
509 int8_t rb_sb = Rb.uq<hi:lo>;
510 temp = ((temp << 8)
511 | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
512 : Rb.uq<hi:lo>));
513 hi -= 8;
514 lo -= 8;
515 }
516 Rc = temp;
517 }});
518
519 0x3f: maxsw4({{
520 uint64_t temp = 0;
521 int hi = 63;
522 int lo = 48;
523 for (int i = 3; i >= 0; --i) {
524 int16_t ra_sw = Ra.uq<hi:lo>;
525 int16_t rb_sw = Rb.uq<hi:lo>;
526 temp = ((temp << 16)
527 | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
528 : Rb.uq<hi:lo>));
529 hi -= 16;
530 lo -= 16;
531 }
532 Rc = temp;
533 }});
534
535 format BasicOperateWithNopCheck {
536 0x70: decode RB {
537 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
538 }
539 0x78: decode RB {
540 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
541 FloatCvtOp);
542 }
543 }
544 }
545 }
546
547 // Conditional branches.
548 format CondBranch {
549 0x39: beq({{ cond = (Ra == 0); }});
550 0x3d: bne({{ cond = (Ra != 0); }});
551 0x3e: bge({{ cond = (Ra.sq >= 0); }});
552 0x3f: bgt({{ cond = (Ra.sq > 0); }});
553 0x3b: ble({{ cond = (Ra.sq <= 0); }});
554 0x3a: blt({{ cond = (Ra.sq < 0); }});
555 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
556 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
557
558 0x31: fbeq({{ cond = (Fa == 0); }});
559 0x35: fbne({{ cond = (Fa != 0); }});
560 0x36: fbge({{ cond = (Fa >= 0); }});
561 0x37: fbgt({{ cond = (Fa > 0); }});
562 0x33: fble({{ cond = (Fa <= 0); }});
563 0x32: fblt({{ cond = (Fa < 0); }});
564 }
565
566 // unconditional branches
567 format UncondBranch {
568 0x30: br();
569 0x34: bsr(IsCall);
570 }
571
572 // indirect branches
573 0x1a: decode JMPFUNC {
574 format Jump {
575 0: jmp();
576 1: jsr(IsCall);
577 2: ret(IsReturn);
578 3: jsr_coroutine(IsCall, IsReturn);
579 }
580 }
581
582 // Square root and integer-to-FP moves
583 0x14: decode FP_SHORTFUNC {
584 // Integer to FP register moves must have RB == 31
585 0x4: decode RB {
586 31: decode FP_FULLFUNC {
587 format BasicOperateWithNopCheck {
588 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
589 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
590 0x014: FailUnimpl::itoff(); // VAX-format conversion
591 }
592 }
593 }
594
595 // Square root instructions must have FA == 31
596 0xb: decode FA {
597 31: decode FP_TYPEFUNC {
598 format FloatingPointOperate {
599 #if SS_COMPATIBLE_FP
600 0x0b: sqrts({{
601 if (Fb < 0.0)
602 fault = new ArithmeticFault;
603 Fc = sqrt(Fb);
604 }}, FloatSqrtOp);
605 #else
606 0x0b: sqrts({{
607 if (Fb.sf < 0.0)
608 fault = new ArithmeticFault;
609 Fc.sf = sqrt(Fb.sf);
610 }}, FloatSqrtOp);
611 #endif
612 0x2b: sqrtt({{
613 if (Fb < 0.0)
614 fault = new ArithmeticFault;
615 Fc = sqrt(Fb);
616 }}, FloatSqrtOp);
617 }
618 }
619 }
620
621 // VAX-format sqrtf and sqrtg are not implemented
622 0xa: FailUnimpl::sqrtfg();
623 }
624
625 // IEEE floating point
626 0x16: decode FP_SHORTFUNC_TOP2 {
627 // The top two bits of the short function code break this
628 // space into four groups: binary ops, compares, reserved, and
629 // conversions. See Table 4-12 of AHB. There are different
630 // special cases in these different groups, so we decode on
631 // these top two bits first just to select a decode strategy.
632 // Most of these instructions may have various trapping and
633 // rounding mode flags set; these are decoded in the
634 // FloatingPointDecode template used by the
635 // FloatingPointOperate format.
636
637 // add/sub/mul/div: just decode on the short function code
638 // and source type. All valid trapping and rounding modes apply.
639 0: decode FP_TRAPMODE {
640 // check for valid trapping modes here
641 0,1,5,7: decode FP_TYPEFUNC {
642 format FloatingPointOperate {
643 #if SS_COMPATIBLE_FP
644 0x00: adds({{ Fc = Fa + Fb; }});
645 0x01: subs({{ Fc = Fa - Fb; }});
646 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
647 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
648 #else
649 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
650 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
651 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
652 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
653 #endif
654
655 0x20: addt({{ Fc = Fa + Fb; }});
656 0x21: subt({{ Fc = Fa - Fb; }});
657 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
658 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
659 }
660 }
661 }
662
663 // Floating-point compare instructions must have the default
664 // rounding mode, and may use the default trapping mode or
665 // /SU. Both trapping modes are treated the same by M5; the
666 // only difference on the real hardware (as far a I can tell)
667 // is that without /SU you'd get an imprecise trap if you
668 // tried to compare a NaN with something else (instead of an
669 // "unordered" result).
670 1: decode FP_FULLFUNC {
671 format BasicOperateWithNopCheck {
672 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
673 FloatCmpOp);
674 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
675 FloatCmpOp);
676 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
677 FloatCmpOp);
678 0x0a4, 0x5a4: cmptun({{ // unordered
679 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
680 }}, FloatCmpOp);
681 }
682 }
683
684 // The FP-to-integer and integer-to-FP conversion insts
685 // require that FA be 31.
686 3: decode FA {
687 31: decode FP_TYPEFUNC {
688 format FloatingPointOperate {
689 0x2f: decode FP_ROUNDMODE {
690 format FPFixedRounding {
691 // "chopped" i.e. round toward zero
692 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
693 Chopped);
694 // round to minus infinity
695 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
696 MinusInfinity);
697 }
698 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
699 }
700
701 // The cvtts opcode is overloaded to be cvtst if the trap
702 // mode is 2 or 6 (which are not valid otherwise)
703 0x2c: decode FP_FULLFUNC {
704 format BasicOperateWithNopCheck {
705 // trap on denorm version "cvtst/s" is
706 // simulated same as cvtst
707 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
708 }
709 default: cvtts({{ Fc.sf = Fb; }});
710 }
711
712 // The trapping mode for integer-to-FP conversions
713 // must be /SUI or nothing; /U and /SU are not
714 // allowed. The full set of rounding modes are
715 // supported though.
716 0x3c: decode FP_TRAPMODE {
717 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
718 }
719 0x3e: decode FP_TRAPMODE {
720 0,7: cvtqt({{ Fc = Fb.sq; }});
721 }
722 }
723 }
724 }
725 }
726
727 // misc FP operate
728 0x17: decode FP_FULLFUNC {
729 format BasicOperateWithNopCheck {
730 0x010: cvtlq({{
731 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
732 }});
733 0x030: cvtql({{
734 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
735 }});
736
737 // We treat the precise & imprecise trapping versions of
738 // cvtql identically.
739 0x130, 0x530: cvtqlv({{
740 // To avoid overflow, all the upper 32 bits must match
741 // the sign bit of the lower 32. We code this as
742 // checking the upper 33 bits for all 0s or all 1s.
743 uint64_t sign_bits = Fb.uq<63:31>;
744 if (sign_bits != 0 && sign_bits != mask(33))
745 fault = new IntegerOverflowFault;
746 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
747 }});
748
749 0x020: cpys({{ // copy sign
750 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
751 }});
752 0x021: cpysn({{ // copy sign negated
753 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
754 }});
755 0x022: cpyse({{ // copy sign and exponent
756 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
757 }});
758
759 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
760 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
761 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
762 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
763 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
764 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
765
766 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
767 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
768 }
769 }
770
771 // miscellaneous mem-format ops
772 0x18: decode MEMFUNC {
773 format WarnUnimpl {
774 0x8000: fetch();
775 0xa000: fetch_m();
776 0xe800: ecb();
777 }
778
779 format MiscPrefetch {
780 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
781 {{ ; }},
782 mem_flags = PREFETCH);
783 }
784
785 format BasicOperate {
786 0xc000: rpcc({{
787 #if FULL_SYSTEM
788 /* Rb is a fake dependency so here is a fun way to get
789 * the parser to understand that.
790 */
791 Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
792
793 #else
794 Ra = curTick;
795 #endif
796 }}, IsUnverifiable);
797
798 // All of the barrier instructions below do nothing in
799 // their execute() methods (hence the empty code blocks).
800 // All of their functionality is hard-coded in the
801 // pipeline based on the flags IsSerializing,
802 // IsMemBarrier, and IsWriteBarrier. In the current
803 // detailed CPU model, the execute() function only gets
804 // called at fetch, so there's no way to generate pipeline
805 // behavior at any other stage. Once we go to an
806 // exec-in-exec CPU model we should be able to get rid of
807 // these flags and implement this behavior via the
808 // execute() methods.
809
810 // trapb is just a barrier on integer traps, where excb is
811 // a barrier on integer and FP traps. "EXCB is thus a
812 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
813 // them the same though.
814 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
815 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
816 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
817 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
818 }
819
820 #if FULL_SYSTEM
821 format BasicOperate {
822 0xe000: rc({{
823 Ra = IntrFlag;
824 IntrFlag = 0;
825 }}, IsNonSpeculative, IsUnverifiable);
826 0xf000: rs({{
827 Ra = IntrFlag;
828 IntrFlag = 1;
829 }}, IsNonSpeculative, IsUnverifiable);
830 }
831 #else
832 format FailUnimpl {
833 0xe000: rc();
834 0xf000: rs();
835 }
836 #endif
837 }
838
839 #if FULL_SYSTEM
840 0x00: CallPal::call_pal({{
841 if (!palValid ||
842 (palPriv
843 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
844 // invalid pal function code, or attempt to do privileged
845 // PAL call in non-kernel mode
846 fault = new UnimplementedOpcodeFault;
847 } else {
848 // check to see if simulator wants to do something special
849 // on this PAL call (including maybe suppress it)
850 bool dopal = xc->simPalCheck(palFunc);
851
852 if (dopal) {
853 xc->setMiscReg(IPR_EXC_ADDR, NPC);
854 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
855 }
856 }
857 }}, IsNonSpeculative);
858 #else
859 0x00: decode PALFUNC {
860 format EmulatedCallPal {
861 0x00: halt ({{
862 exitSimLoop("halt instruction encountered");
863 }}, IsNonSpeculative);
864 0x83: callsys({{
865 xc->syscall(R0);
866 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
867 // Read uniq reg into ABI return value register (r0)
868 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
869 // Write uniq reg with value from ABI arg register (r16)
870 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
871 }
872 }
873 #endif
874
875 #if FULL_SYSTEM
876 0x1b: decode PALMODE {
877 0: OpcdecFault::hw_st_quad();
878 1: decode HW_LDST_QUAD {
879 format HwLoad {
880 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
881 L, IsSerializing, IsSerializeBefore);
882 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
883 Q, IsSerializing, IsSerializeBefore);
884 }
885 }
886 }
887
888 0x1f: decode PALMODE {
889 0: OpcdecFault::hw_st_cond();
890 format HwStore {
891 1: decode HW_LDST_COND {
892 0: decode HW_LDST_QUAD {
893 0: hw_st({{ EA = (Rb + disp) & ~3; }},
894 {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
895 1: hw_st({{ EA = (Rb + disp) & ~7; }},
896 {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
897 }
898
899 1: FailUnimpl::hw_st_cond();
900 }
901 }
902 }
903
904 0x19: decode PALMODE {
905 0: OpcdecFault::hw_mfpr();
906 format HwMoveIPR {
907 1: hw_mfpr({{
908 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
909 IprToMiscRegIndex[ipr_index] : -1;
910 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
911 miscRegIndex >= NumInternalProcRegs)
912 fault = new UnimplementedOpcodeFault;
913 else
914 Ra = xc->readMiscReg(miscRegIndex);
915 }}, IsIprAccess);
916 }
917 }
918
919 0x1d: decode PALMODE {
920 0: OpcdecFault::hw_mtpr();
921 format HwMoveIPR {
922 1: hw_mtpr({{
923 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
924 IprToMiscRegIndex[ipr_index] : -1;
925 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
926 miscRegIndex >= NumInternalProcRegs)
927 fault = new UnimplementedOpcodeFault;
928 else
929 xc->setMiscReg(miscRegIndex, Ra);
930 if (traceData) { traceData->setData(Ra); }
931 }}, IsIprAccess);
932 }
933 }
934
935 0x1e: decode PALMODE {
936 0: OpcdecFault::hw_rei();
937 format BasicOperate {
938 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
939 }
940 }
941
942 #endif
943
944 format BasicOperate {
945 // M5 special opcodes use the reserved 0x01 opcode space
946 0x01: decode M5FUNC {
947 #if FULL_SYSTEM
948 0x00: arm({{
949 PseudoInst::arm(xc->tcBase());
950 }}, IsNonSpeculative);
951 0x01: quiesce({{
952 PseudoInst::quiesce(xc->tcBase());
953 }}, IsNonSpeculative, IsQuiesce);
954 0x02: quiesceNs({{
955 PseudoInst::quiesceNs(xc->tcBase(), R16);
956 }}, IsNonSpeculative, IsQuiesce);
957 0x03: quiesceCycles({{
958 PseudoInst::quiesceCycles(xc->tcBase(), R16);
959 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
960 0x04: quiesceTime({{
961 R0 = PseudoInst::quiesceTime(xc->tcBase());
962 }}, IsNonSpeculative, IsUnverifiable);
963 #endif
964 0x07: rpns({{
965 R0 = PseudoInst::rpns(xc->tcBase());
966 }}, IsNonSpeculative, IsUnverifiable);
967 0x09: wakeCPU({{
968 PseudoInst::wakeCPU(xc->tcBase(), R16);
969 }}, IsNonSpeculative, IsUnverifiable);
970 0x10: deprecated_ivlb({{
971 warn_once("Obsolete M5 ivlb instruction encountered.\n");
972 }});
973 0x11: deprecated_ivle({{
974 warn_once("Obsolete M5 ivlb instruction encountered.\n");
975 }});
976 0x20: deprecated_exit ({{
977 warn_once("deprecated M5 exit instruction encountered.\n");
978 PseudoInst::m5exit(xc->tcBase(), 0);
979 }}, No_OpClass, IsNonSpeculative);
980 0x21: m5exit({{
981 PseudoInst::m5exit(xc->tcBase(), R16);
982 }}, No_OpClass, IsNonSpeculative);
983 #if FULL_SYSTEM
984 0x31: loadsymbol({{
985 PseudoInst::loadsymbol(xc->tcBase());
986 }}, No_OpClass, IsNonSpeculative);
987 0x30: initparam({{
988 Ra = xc->tcBase()->getCpuPtr()->system->init_param;
989 }});
990 #endif
991 0x40: resetstats({{
992 PseudoInst::resetstats(xc->tcBase(), R16, R17);
993 }}, IsNonSpeculative);
994 0x41: dumpstats({{
995 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
996 }}, IsNonSpeculative);
997 0x42: dumpresetstats({{
998 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
999 }}, IsNonSpeculative);
1000 0x43: m5checkpoint({{
1001 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
1002 }}, IsNonSpeculative);
1003 #if FULL_SYSTEM
1004 0x50: m5readfile({{
1005 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
1006 }}, IsNonSpeculative);
1007 #endif
1008 0x51: m5break({{
1009 PseudoInst::debugbreak(xc->tcBase());
1010 }}, IsNonSpeculative);
1011 0x52: m5switchcpu({{
1012 PseudoInst::switchcpu(xc->tcBase());
1013 }}, IsNonSpeculative);
1014 #if FULL_SYSTEM
1015 0x53: m5addsymbol({{
1016 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
1017 }}, IsNonSpeculative);
1018 #endif
1019 0x54: m5panic({{
1020 panic("M5 panic instruction called at pc = %#x.", PC);
1021 }}, IsNonSpeculative);
1022 #define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
1023 0x55: decode RA {
1024 0x00: m5a_old({{
1025 panic("Deprecated M5 annotate instruction executed "
1026 "at pc = %#x\n", PC);
1027 }}, IsNonSpeculative);
1028 0x01: m5a_bsm({{
1029 CPANN(swSmBegin);
1030 }}, IsNonSpeculative);
1031 0x02: m5a_esm({{
1032 CPANN(swSmEnd);
1033 }}, IsNonSpeculative);
1034 0x03: m5a_begin({{
1035 CPANN(swExplictBegin);
1036 }}, IsNonSpeculative);
1037 0x04: m5a_end({{
1038 CPANN(swEnd);
1039 }}, IsNonSpeculative);
1040 0x06: m5a_q({{
1041 CPANN(swQ);
1042 }}, IsNonSpeculative);
1043 0x07: m5a_dq({{
1044 CPANN(swDq);
1045 }}, IsNonSpeculative);
1046 0x08: m5a_wf({{
1047 CPANN(swWf);
1048 }}, IsNonSpeculative);
1049 0x09: m5a_we({{
1050 CPANN(swWe);
1051 }}, IsNonSpeculative);
1052 0x0C: m5a_sq({{
1053 CPANN(swSq);
1054 }}, IsNonSpeculative);
1055 0x0D: m5a_aq({{
1056 CPANN(swAq);
1057 }}, IsNonSpeculative);
1058 0x0E: m5a_pq({{
1059 CPANN(swPq);
1060 }}, IsNonSpeculative);
1061 0x0F: m5a_l({{
1062 CPANN(swLink);
1063 }}, IsNonSpeculative);
1064 0x10: m5a_identify({{
1065 CPANN(swIdentify);
1066 }}, IsNonSpeculative);
1067 0x11: m5a_getid({{
1068 R0 = CPANN(swGetId);
1069 }}, IsNonSpeculative);
1070 0x13: m5a_scl({{
1071 CPANN(swSyscallLink);
1072 }}, IsNonSpeculative);
1073 0x14: m5a_rq({{
1074 CPANN(swRq);
1075 }}, IsNonSpeculative);
1076 } // M5 Annotate Operations
1077 #undef CPANN
1078 0x56: m5reserved2({{
1079 warn("M5 reserved opcode ignored");
1080 }}, IsNonSpeculative);
1081 0x57: m5reserved3({{
1082 warn("M5 reserved opcode ignored");
1083 }}, IsNonSpeculative);
1084 0x58: m5reserved4({{
1085 warn("M5 reserved opcode ignored");
1086 }}, IsNonSpeculative);
1087 0x59: m5reserved5({{
1088 warn("M5 reserved opcode ignored");
1089 }}, IsNonSpeculative);
1090 }
1091 }
1092 }