3 // Copyright (c) 2003-2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
31 ////////////////////////////////////////////////////////////////////
33 // The actual decoder specification
36 decode OPCODE default Unknown::unknown() {
39 0x08: lda({{ Ra = Rb + disp; }});
40 0x09: ldah({{ Ra = Rb + (disp << 16); }});
44 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47 0x23: ldt({{ Fa = Mem.df; }});
48 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
49 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
51 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
52 {{ fault = xc->copySrcTranslate(EA); }},
53 inst_flags = [IsMemRef, IsLoad, IsCopy]);
57 format LoadOrPrefetch {
58 0x28: ldl({{ Ra.sl = Mem.sl; }});
59 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
60 // IsFloating flag on lds gets the prefetch to disassemble
61 // using f31 instead of r31... funcitonally it's unnecessary
62 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
63 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
67 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
68 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
69 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
70 0x2d: stq({{ Mem.uq = Ra.uq; }});
71 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
72 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
73 0x27: stt({{ Mem.df = Fa; }});
75 0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
76 {{ fault = xc->copy(EA); }},
77 inst_flags = [IsMemRef, IsStore, IsCopy]);
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
84 uint64_t tmp = write_result;
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
88 xc->setStCondFailures(0);
90 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
91 0x2f: stq_c({{ Mem.uq = Ra; }},
93 uint64_t tmp = write_result;
94 // If the write operation returns 0 or 1, then
95 // this was a conventional store conditional,
96 // and the value indicates the success/failure
97 // of the operation. If another value is
98 // returned, then this was a Turbolaser
99 // mailbox access, and we don't update the
100 // result register at all.
101 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
103 // clear failure counter... this is
104 // non-architectural and for debugging
106 xc->setStCondFailures(0);
108 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
111 format IntegerOperate {
113 0x10: decode INTFUNC { // integer arithmetic operations
115 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
117 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
118 // signed overflow occurs when operands have same sign
119 // and sign of result does not match.
120 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
121 fault = new IntegerOverflowFault;
124 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
125 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
127 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
129 uint64_t tmp = Ra + Rb_or_imm;
130 // signed overflow occurs when operands have same sign
131 // and sign of result does not match.
132 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
133 fault = new IntegerOverflowFault;
136 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
137 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
139 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
141 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
142 // signed overflow detection is same as for add,
143 // except we need to look at the *complemented*
144 // sign bit of the subtrahend (Rb), i.e., if the initial
145 // signs are the *same* then no overflow can occur
146 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
147 fault = new IntegerOverflowFault;
150 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
151 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
153 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
155 uint64_t tmp = Ra - Rb_or_imm;
156 // signed overflow detection is same as for add,
157 // except we need to look at the *complemented*
158 // sign bit of the subtrahend (Rb), i.e., if the initial
159 // signs are the *same* then no overflow can occur
160 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
161 fault = new IntegerOverflowFault;
164 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
165 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
167 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
168 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
169 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
170 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
171 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
177 for (int i = 0; i < 8; ++i) {
178 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
186 0x11: decode INTFUNC { // integer logical operations
188 0x00: and({{ Rc = Ra & Rb_or_imm; }});
189 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
190 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
191 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
192 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
193 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
196 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
197 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
198 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
199 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
200 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
201 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
202 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
203 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
205 // For AMASK, RA must be R31.
207 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
210 // For IMPLVER, RA must be R31 and the B operand
211 // must be the immediate value 1.
215 // return EV5 for FULL_SYSTEM and EV6 otherwise
228 // The mysterious 11.25...
229 0x25: WarnUnimpl::eleven25();
233 0x12: decode INTFUNC {
234 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
235 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
236 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
238 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
239 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
240 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
241 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
244 int bv = Rb_or_imm<2:0>;
245 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
248 int bv = Rb_or_imm<2:0>;
249 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
252 int bv = Rb_or_imm<2:0>;
253 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
256 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
257 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
258 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
259 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
262 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
264 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
266 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
268 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
269 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
270 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
271 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
274 int bv = Rb_or_imm<2:0>;
275 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
278 int bv = Rb_or_imm<2:0>;
279 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
282 int bv = Rb_or_imm<2:0>;
283 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
287 uint64_t zapmask = 0;
288 for (int i = 0; i < 8; ++i) {
290 zapmask |= (mask(8) << (i * 8));
295 uint64_t zapmask = 0;
296 for (int i = 0; i < 8; ++i) {
298 zapmask |= (mask(8) << (i * 8));
304 0x13: decode INTFUNC { // integer multiplies
305 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
306 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
309 mul128(Ra, Rb_or_imm, hi, lo);
313 // 32-bit multiply with trap on overflow
314 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
315 int64_t Rbx = Rb_or_imm.sl;
316 int64_t tmp = Rax * Rbx;
317 // To avoid overflow, all the upper 32 bits must match
318 // the sign bit of the lower 32. We code this as
319 // checking the upper 33 bits for all 0s or all 1s.
320 uint64_t sign_bits = tmp<63:31>;
321 if (sign_bits != 0 && sign_bits != mask(33))
322 fault = new IntegerOverflowFault;
326 // 64-bit multiply with trap on overflow
328 mul128(Ra, Rb_or_imm, hi, lo);
329 // all the upper 64 bits must match the sign bit of
331 if (!((hi == 0 && lo<63:> == 0) ||
332 (hi == mask(64) && lo<63:> == 1)))
333 fault = new IntegerOverflowFault;
338 0x1c: decode INTFUNC {
339 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
340 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
344 if (temp<63:32>) temp >>= 32; else count += 32;
345 if (temp<31:16>) temp >>= 16; else count += 16;
346 if (temp<15:8>) temp >>= 8; else count += 8;
347 if (temp<7:4>) temp >>= 4; else count += 4;
348 if (temp<3:2>) temp >>= 2; else count += 2;
349 if (temp<1:1>) temp >>= 1; else count += 1;
350 if ((temp<0:0>) != 0x1) count += 1;
357 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
358 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
359 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
360 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
361 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
362 if (!(temp<0:0> & ULL(0x1))) count += 1;
383 format BasicOperateWithNopCheck {
385 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
388 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
395 // Conditional branches.
397 0x39: beq({{ cond = (Ra == 0); }});
398 0x3d: bne({{ cond = (Ra != 0); }});
399 0x3e: bge({{ cond = (Ra.sq >= 0); }});
400 0x3f: bgt({{ cond = (Ra.sq > 0); }});
401 0x3b: ble({{ cond = (Ra.sq <= 0); }});
402 0x3a: blt({{ cond = (Ra.sq < 0); }});
403 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
404 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
406 0x31: fbeq({{ cond = (Fa == 0); }});
407 0x35: fbne({{ cond = (Fa != 0); }});
408 0x36: fbge({{ cond = (Fa >= 0); }});
409 0x37: fbgt({{ cond = (Fa > 0); }});
410 0x33: fble({{ cond = (Fa <= 0); }});
411 0x32: fblt({{ cond = (Fa < 0); }});
414 // unconditional branches
415 format UncondBranch {
421 0x1a: decode JMPFUNC {
426 3: jsr_coroutine(IsCall, IsReturn);
430 // Square root and integer-to-FP moves
431 0x14: decode FP_SHORTFUNC {
432 // Integer to FP register moves must have RB == 31
434 31: decode FP_FULLFUNC {
435 format BasicOperateWithNopCheck {
436 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
437 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
438 0x014: FailUnimpl::itoff(); // VAX-format conversion
443 // Square root instructions must have FA == 31
445 31: decode FP_TYPEFUNC {
446 format FloatingPointOperate {
450 fault = new ArithmeticFault;
456 fault = new ArithmeticFault;
462 fault = new ArithmeticFault;
469 // VAX-format sqrtf and sqrtg are not implemented
470 0xa: FailUnimpl::sqrtfg();
473 // IEEE floating point
474 0x16: decode FP_SHORTFUNC_TOP2 {
475 // The top two bits of the short function code break this
476 // space into four groups: binary ops, compares, reserved, and
477 // conversions. See Table 4-12 of AHB. There are different
478 // special cases in these different groups, so we decode on
479 // these top two bits first just to select a decode strategy.
480 // Most of these instructions may have various trapping and
481 // rounding mode flags set; these are decoded in the
482 // FloatingPointDecode template used by the
483 // FloatingPointOperate format.
485 // add/sub/mul/div: just decode on the short function code
486 // and source type. All valid trapping and rounding modes apply.
487 0: decode FP_TRAPMODE {
488 // check for valid trapping modes here
489 0,1,5,7: decode FP_TYPEFUNC {
490 format FloatingPointOperate {
492 0x00: adds({{ Fc = Fa + Fb; }});
493 0x01: subs({{ Fc = Fa - Fb; }});
494 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
495 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
497 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
498 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
499 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
500 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
503 0x20: addt({{ Fc = Fa + Fb; }});
504 0x21: subt({{ Fc = Fa - Fb; }});
505 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
506 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
511 // Floating-point compare instructions must have the default
512 // rounding mode, and may use the default trapping mode or
513 // /SU. Both trapping modes are treated the same by M5; the
514 // only difference on the real hardware (as far a I can tell)
515 // is that without /SU you'd get an imprecise trap if you
516 // tried to compare a NaN with something else (instead of an
517 // "unordered" result).
518 1: decode FP_FULLFUNC {
519 format BasicOperateWithNopCheck {
520 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
522 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
524 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
526 0x0a4, 0x5a4: cmptun({{ // unordered
527 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
532 // The FP-to-integer and integer-to-FP conversion insts
533 // require that FA be 31.
535 31: decode FP_TYPEFUNC {
536 format FloatingPointOperate {
537 0x2f: decode FP_ROUNDMODE {
538 format FPFixedRounding {
539 // "chopped" i.e. round toward zero
540 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
542 // round to minus infinity
543 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
546 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
549 // The cvtts opcode is overloaded to be cvtst if the trap
550 // mode is 2 or 6 (which are not valid otherwise)
551 0x2c: decode FP_FULLFUNC {
552 format BasicOperateWithNopCheck {
553 // trap on denorm version "cvtst/s" is
554 // simulated same as cvtst
555 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
557 default: cvtts({{ Fc.sf = Fb; }});
560 // The trapping mode for integer-to-FP conversions
561 // must be /SUI or nothing; /U and /SU are not
562 // allowed. The full set of rounding modes are
564 0x3c: decode FP_TRAPMODE {
565 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
567 0x3e: decode FP_TRAPMODE {
568 0,7: cvtqt({{ Fc = Fb.sq; }});
576 0x17: decode FP_FULLFUNC {
577 format BasicOperateWithNopCheck {
579 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
582 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
585 // We treat the precise & imprecise trapping versions of
586 // cvtql identically.
587 0x130, 0x530: cvtqlv({{
588 // To avoid overflow, all the upper 32 bits must match
589 // the sign bit of the lower 32. We code this as
590 // checking the upper 33 bits for all 0s or all 1s.
591 uint64_t sign_bits = Fb.uq<63:31>;
592 if (sign_bits != 0 && sign_bits != mask(33))
593 fault = new IntegerOverflowFault;
594 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
597 0x020: cpys({{ // copy sign
598 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
600 0x021: cpysn({{ // copy sign negated
601 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
603 0x022: cpyse({{ // copy sign and exponent
604 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
607 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
608 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
609 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
610 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
611 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
612 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
614 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
615 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
619 // miscellaneous mem-format ops
620 0x18: decode MEMFUNC {
627 format MiscPrefetch {
628 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
629 {{ xc->writeHint(EA, 64, memAccessFlags); }},
630 mem_flags = NO_FAULT,
631 inst_flags = [IsMemRef, IsDataPrefetch,
632 IsStore, MemWriteOp]);
635 format BasicOperate {
638 /* Rb is a fake dependency so here is a fun way to get
639 * the parser to understand that.
641 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
648 // All of the barrier instructions below do nothing in
649 // their execute() methods (hence the empty code blocks).
650 // All of their functionality is hard-coded in the
651 // pipeline based on the flags IsSerializing,
652 // IsMemBarrier, and IsWriteBarrier. In the current
653 // detailed CPU model, the execute() function only gets
654 // called at fetch, so there's no way to generate pipeline
655 // behavior at any other stage. Once we go to an
656 // exec-in-exec CPU model we should be able to get rid of
657 // these flags and implement this behavior via the
658 // execute() methods.
660 // trapb is just a barrier on integer traps, where excb is
661 // a barrier on integer and FP traps. "EXCB is thus a
662 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
663 // them the same though.
664 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
665 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
666 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
667 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
671 format BasicOperate {
675 }}, IsNonSpeculative, IsUnverifiable);
679 }}, IsNonSpeculative, IsUnverifiable);
690 0x00: CallPal::call_pal({{
693 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
694 // invalid pal function code, or attempt to do privileged
695 // PAL call in non-kernel mode
696 fault = new UnimplementedOpcodeFault;
699 // check to see if simulator wants to do something special
700 // on this PAL call (including maybe suppress it)
701 bool dopal = xc->simPalCheck(palFunc);
704 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
705 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
708 }}, IsNonSpeculative);
710 0x00: decode PALFUNC {
711 format EmulatedCallPal {
713 exitSimLoop("halt instruction encountered");
714 }}, IsNonSpeculative);
717 }}, IsSerializeAfter, IsNonSpeculative);
718 // Read uniq reg into ABI return value register (r0)
719 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
720 // Write uniq reg with value from ABI arg register (r16)
721 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
727 0x1b: decode PALMODE {
728 0: OpcdecFault::hw_st_quad();
729 1: decode HW_LDST_QUAD {
731 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
732 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
737 0x1f: decode PALMODE {
738 0: OpcdecFault::hw_st_cond();
740 1: decode HW_LDST_COND {
741 0: decode HW_LDST_QUAD {
742 0: hw_st({{ EA = (Rb + disp) & ~3; }},
743 {{ Mem.ul = Ra<31:0>; }}, L);
744 1: hw_st({{ EA = (Rb + disp) & ~7; }},
745 {{ Mem.uq = Ra.uq; }}, Q);
748 1: FailUnimpl::hw_st_cond();
753 0x19: decode PALMODE {
754 0: OpcdecFault::hw_mfpr();
757 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
758 IprToMiscRegIndex[ipr_index] : -1;
759 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
760 miscRegIndex >= NumInternalProcRegs)
761 fault = new UnimplementedOpcodeFault;
763 Ra = xc->readMiscRegWithEffect(miscRegIndex);
768 0x1d: decode PALMODE {
769 0: OpcdecFault::hw_mtpr();
772 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
773 IprToMiscRegIndex[ipr_index] : -1;
774 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
775 miscRegIndex >= NumInternalProcRegs)
776 fault = new UnimplementedOpcodeFault;
778 xc->setMiscRegWithEffect(miscRegIndex, Ra);
779 if (traceData) { traceData->setData(Ra); }
784 format BasicOperate {
785 0x1e: decode PALMODE {
786 0: OpcdecFault::hw_rei();
787 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
790 // M5 special opcodes use the reserved 0x01 opcode space
791 0x01: decode M5FUNC {
793 AlphaPseudo::arm(xc->tcBase());
794 }}, IsNonSpeculative);
796 AlphaPseudo::quiesce(xc->tcBase());
797 }}, IsNonSpeculative, IsQuiesce);
799 AlphaPseudo::quiesceNs(xc->tcBase(), R16);
800 }}, IsNonSpeculative, IsQuiesce);
801 0x03: quiesceCycles({{
802 AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
803 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
805 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
806 }}, IsNonSpeculative, IsUnverifiable);
808 warn_once("Obsolete M5 instruction ivlb encountered.\n");
811 warn_once("Obsolete M5 instruction ivlb encountered.\n");
814 AlphaPseudo::m5exit_old(xc->tcBase());
815 }}, No_OpClass, IsNonSpeculative);
817 AlphaPseudo::m5exit(xc->tcBase(), R16);
818 }}, No_OpClass, IsNonSpeculative);
820 AlphaPseudo::loadsymbol(xc->tcBase());
821 }}, No_OpClass, IsNonSpeculative);
822 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
824 AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
825 }}, IsNonSpeculative);
827 AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
828 }}, IsNonSpeculative);
829 0x42: dumpresetstats({{
830 AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
831 }}, IsNonSpeculative);
832 0x43: m5checkpoint({{
833 AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
834 }}, IsNonSpeculative);
836 R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
837 }}, IsNonSpeculative);
839 AlphaPseudo::debugbreak(xc->tcBase());
840 }}, IsNonSpeculative);
842 AlphaPseudo::switchcpu(xc->tcBase());
843 }}, IsNonSpeculative);
845 AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
846 }}, IsNonSpeculative);
848 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
849 }}, IsNonSpeculative);
851 AlphaPseudo::anBegin(xc->tcBase(), R16);
852 }}, IsNonSpeculative);
854 AlphaPseudo::anWait(xc->tcBase(), R16, R17);
855 }}, IsNonSpeculative);