3 // Copyright (c) 2003-2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
31 ////////////////////////////////////////////////////////////////////
33 // The actual decoder specification
36 decode OPCODE default Unknown::unknown() {
39 0x08: lda({{ Ra = Rb + disp; }});
40 0x09: ldah({{ Ra = Rb + (disp << 16); }});
44 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47 0x23: ldt({{ Fa = Mem.df; }});
48 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
49 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
51 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
52 {{ fault = xc->copySrcTranslate(EA); }},
53 inst_flags = [IsMemRef, IsLoad, IsCopy]);
57 format LoadOrPrefetch {
58 0x28: ldl({{ Ra.sl = Mem.sl; }});
59 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
60 // IsFloating flag on lds gets the prefetch to disassemble
61 // using f31 instead of r31... funcitonally it's unnecessary
62 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
63 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
67 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
68 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
69 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
70 0x2d: stq({{ Mem.uq = Ra.uq; }});
71 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
72 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
73 0x27: stt({{ Mem.df = Fa; }});
75 0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
76 {{ fault = xc->copy(EA); }},
77 inst_flags = [IsMemRef, IsStore, IsCopy]);
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
84 uint64_t tmp = write_result;
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
88 0x2f: stq_c({{ Mem.uq = Ra; }},
90 uint64_t tmp = write_result;
91 // If the write operation returns 0 or 1, then
92 // this was a conventional store conditional,
93 // and the value indicates the success/failure
94 // of the operation. If another value is
95 // returned, then this was a Turbolaser
96 // mailbox access, and we don't update the
97 // result register at all.
98 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
99 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
102 format IntegerOperate {
104 0x10: decode INTFUNC { // integer arithmetic operations
106 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
108 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
109 // signed overflow occurs when operands have same sign
110 // and sign of result does not match.
111 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
112 fault = new IntegerOverflowFault;
115 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
116 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
118 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
120 uint64_t tmp = Ra + Rb_or_imm;
121 // signed overflow occurs when operands have same sign
122 // and sign of result does not match.
123 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
124 fault = new IntegerOverflowFault;
127 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
128 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
130 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
132 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
133 // signed overflow detection is same as for add,
134 // except we need to look at the *complemented*
135 // sign bit of the subtrahend (Rb), i.e., if the initial
136 // signs are the *same* then no overflow can occur
137 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
138 fault = new IntegerOverflowFault;
141 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
142 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
144 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
146 uint64_t tmp = Ra - Rb_or_imm;
147 // signed overflow detection is same as for add,
148 // except we need to look at the *complemented*
149 // sign bit of the subtrahend (Rb), i.e., if the initial
150 // signs are the *same* then no overflow can occur
151 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
152 fault = new IntegerOverflowFault;
155 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
156 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
158 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
159 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
160 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
161 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
162 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
168 for (int i = 0; i < 8; ++i) {
169 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
177 0x11: decode INTFUNC { // integer logical operations
179 0x00: and({{ Rc = Ra & Rb_or_imm; }});
180 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
181 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
182 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
183 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
184 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
187 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
188 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
189 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
190 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
191 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
192 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
193 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
194 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
196 // For AMASK, RA must be R31.
198 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
201 // For IMPLVER, RA must be R31 and the B operand
202 // must be the immediate value 1.
206 // return EV5 for FULL_SYSTEM and EV6 otherwise
219 // The mysterious 11.25...
220 0x25: WarnUnimpl::eleven25();
224 0x12: decode INTFUNC {
225 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
226 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
227 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
229 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
230 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
231 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
232 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
235 int bv = Rb_or_imm<2:0>;
236 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
239 int bv = Rb_or_imm<2:0>;
240 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
243 int bv = Rb_or_imm<2:0>;
244 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
247 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
248 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
249 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
250 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
253 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
255 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
257 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
259 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
260 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
261 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
262 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
265 int bv = Rb_or_imm<2:0>;
266 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
269 int bv = Rb_or_imm<2:0>;
270 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
273 int bv = Rb_or_imm<2:0>;
274 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
278 uint64_t zapmask = 0;
279 for (int i = 0; i < 8; ++i) {
281 zapmask |= (mask(8) << (i * 8));
286 uint64_t zapmask = 0;
287 for (int i = 0; i < 8; ++i) {
289 zapmask |= (mask(8) << (i * 8));
295 0x13: decode INTFUNC { // integer multiplies
296 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
297 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
300 mul128(Ra, Rb_or_imm, hi, lo);
304 // 32-bit multiply with trap on overflow
305 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
306 int64_t Rbx = Rb_or_imm.sl;
307 int64_t tmp = Rax * Rbx;
308 // To avoid overflow, all the upper 32 bits must match
309 // the sign bit of the lower 32. We code this as
310 // checking the upper 33 bits for all 0s or all 1s.
311 uint64_t sign_bits = tmp<63:31>;
312 if (sign_bits != 0 && sign_bits != mask(33))
313 fault = new IntegerOverflowFault;
317 // 64-bit multiply with trap on overflow
319 mul128(Ra, Rb_or_imm, hi, lo);
320 // all the upper 64 bits must match the sign bit of
322 if (!((hi == 0 && lo<63:> == 0) ||
323 (hi == mask(64) && lo<63:> == 1)))
324 fault = new IntegerOverflowFault;
329 0x1c: decode INTFUNC {
330 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
331 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
335 if (temp<63:32>) temp >>= 32; else count += 32;
336 if (temp<31:16>) temp >>= 16; else count += 16;
337 if (temp<15:8>) temp >>= 8; else count += 8;
338 if (temp<7:4>) temp >>= 4; else count += 4;
339 if (temp<3:2>) temp >>= 2; else count += 2;
340 if (temp<1:1>) temp >>= 1; else count += 1;
341 if ((temp<0:0>) != 0x1) count += 1;
348 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
349 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
350 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
351 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
352 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
353 if (!(temp<0:0> & ULL(0x1))) count += 1;
374 format BasicOperateWithNopCheck {
376 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
379 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
386 // Conditional branches.
388 0x39: beq({{ cond = (Ra == 0); }});
389 0x3d: bne({{ cond = (Ra != 0); }});
390 0x3e: bge({{ cond = (Ra.sq >= 0); }});
391 0x3f: bgt({{ cond = (Ra.sq > 0); }});
392 0x3b: ble({{ cond = (Ra.sq <= 0); }});
393 0x3a: blt({{ cond = (Ra.sq < 0); }});
394 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
395 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
397 0x31: fbeq({{ cond = (Fa == 0); }});
398 0x35: fbne({{ cond = (Fa != 0); }});
399 0x36: fbge({{ cond = (Fa >= 0); }});
400 0x37: fbgt({{ cond = (Fa > 0); }});
401 0x33: fble({{ cond = (Fa <= 0); }});
402 0x32: fblt({{ cond = (Fa < 0); }});
405 // unconditional branches
406 format UncondBranch {
412 0x1a: decode JMPFUNC {
417 3: jsr_coroutine(IsCall, IsReturn);
421 // Square root and integer-to-FP moves
422 0x14: decode FP_SHORTFUNC {
423 // Integer to FP register moves must have RB == 31
425 31: decode FP_FULLFUNC {
426 format BasicOperateWithNopCheck {
427 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
428 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
429 0x014: FailUnimpl::itoff(); // VAX-format conversion
434 // Square root instructions must have FA == 31
436 31: decode FP_TYPEFUNC {
437 format FloatingPointOperate {
441 fault = new ArithmeticFault;
447 fault = new ArithmeticFault;
453 fault = new ArithmeticFault;
460 // VAX-format sqrtf and sqrtg are not implemented
461 0xa: FailUnimpl::sqrtfg();
464 // IEEE floating point
465 0x16: decode FP_SHORTFUNC_TOP2 {
466 // The top two bits of the short function code break this
467 // space into four groups: binary ops, compares, reserved, and
468 // conversions. See Table 4-12 of AHB. There are different
469 // special cases in these different groups, so we decode on
470 // these top two bits first just to select a decode strategy.
471 // Most of these instructions may have various trapping and
472 // rounding mode flags set; these are decoded in the
473 // FloatingPointDecode template used by the
474 // FloatingPointOperate format.
476 // add/sub/mul/div: just decode on the short function code
477 // and source type. All valid trapping and rounding modes apply.
478 0: decode FP_TRAPMODE {
479 // check for valid trapping modes here
480 0,1,5,7: decode FP_TYPEFUNC {
481 format FloatingPointOperate {
483 0x00: adds({{ Fc = Fa + Fb; }});
484 0x01: subs({{ Fc = Fa - Fb; }});
485 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
486 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
488 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
489 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
490 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
491 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
494 0x20: addt({{ Fc = Fa + Fb; }});
495 0x21: subt({{ Fc = Fa - Fb; }});
496 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
497 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
502 // Floating-point compare instructions must have the default
503 // rounding mode, and may use the default trapping mode or
504 // /SU. Both trapping modes are treated the same by M5; the
505 // only difference on the real hardware (as far a I can tell)
506 // is that without /SU you'd get an imprecise trap if you
507 // tried to compare a NaN with something else (instead of an
508 // "unordered" result).
509 1: decode FP_FULLFUNC {
510 format BasicOperateWithNopCheck {
511 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
513 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
515 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
517 0x0a4, 0x5a4: cmptun({{ // unordered
518 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
523 // The FP-to-integer and integer-to-FP conversion insts
524 // require that FA be 31.
526 31: decode FP_TYPEFUNC {
527 format FloatingPointOperate {
528 0x2f: decode FP_ROUNDMODE {
529 format FPFixedRounding {
530 // "chopped" i.e. round toward zero
531 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
533 // round to minus infinity
534 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
537 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
540 // The cvtts opcode is overloaded to be cvtst if the trap
541 // mode is 2 or 6 (which are not valid otherwise)
542 0x2c: decode FP_FULLFUNC {
543 format BasicOperateWithNopCheck {
544 // trap on denorm version "cvtst/s" is
545 // simulated same as cvtst
546 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
548 default: cvtts({{ Fc.sf = Fb; }});
551 // The trapping mode for integer-to-FP conversions
552 // must be /SUI or nothing; /U and /SU are not
553 // allowed. The full set of rounding modes are
555 0x3c: decode FP_TRAPMODE {
556 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
558 0x3e: decode FP_TRAPMODE {
559 0,7: cvtqt({{ Fc = Fb.sq; }});
567 0x17: decode FP_FULLFUNC {
568 format BasicOperateWithNopCheck {
570 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
573 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
576 // We treat the precise & imprecise trapping versions of
577 // cvtql identically.
578 0x130, 0x530: cvtqlv({{
579 // To avoid overflow, all the upper 32 bits must match
580 // the sign bit of the lower 32. We code this as
581 // checking the upper 33 bits for all 0s or all 1s.
582 uint64_t sign_bits = Fb.uq<63:31>;
583 if (sign_bits != 0 && sign_bits != mask(33))
584 fault = new IntegerOverflowFault;
585 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
588 0x020: cpys({{ // copy sign
589 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
591 0x021: cpysn({{ // copy sign negated
592 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
594 0x022: cpyse({{ // copy sign and exponent
595 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
598 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
599 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
600 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
601 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
602 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
603 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
605 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
606 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
610 // miscellaneous mem-format ops
611 0x18: decode MEMFUNC {
618 format MiscPrefetch {
619 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
620 {{ xc->writeHint(EA, 64, memAccessFlags); }},
621 mem_flags = NO_FAULT,
622 inst_flags = [IsMemRef, IsDataPrefetch,
623 IsStore, MemWriteOp]);
626 format BasicOperate {
629 /* Rb is a fake dependency so here is a fun way to get
630 * the parser to understand that.
632 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
639 // All of the barrier instructions below do nothing in
640 // their execute() methods (hence the empty code blocks).
641 // All of their functionality is hard-coded in the
642 // pipeline based on the flags IsSerializing,
643 // IsMemBarrier, and IsWriteBarrier. In the current
644 // detailed CPU model, the execute() function only gets
645 // called at fetch, so there's no way to generate pipeline
646 // behavior at any other stage. Once we go to an
647 // exec-in-exec CPU model we should be able to get rid of
648 // these flags and implement this behavior via the
649 // execute() methods.
651 // trapb is just a barrier on integer traps, where excb is
652 // a barrier on integer and FP traps. "EXCB is thus a
653 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
654 // them the same though.
655 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
656 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
657 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
658 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
662 format BasicOperate {
666 }}, IsNonSpeculative, IsUnverifiable);
670 }}, IsNonSpeculative, IsUnverifiable);
681 0x00: CallPal::call_pal({{
684 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
685 // invalid pal function code, or attempt to do privileged
686 // PAL call in non-kernel mode
687 fault = new UnimplementedOpcodeFault;
690 // check to see if simulator wants to do something special
691 // on this PAL call (including maybe suppress it)
692 bool dopal = xc->simPalCheck(palFunc);
695 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
696 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
699 }}, IsNonSpeculative);
701 0x00: decode PALFUNC {
702 format EmulatedCallPal {
704 exitSimLoop("halt instruction encountered");
705 }}, IsNonSpeculative);
708 }}, IsSerializeAfter, IsNonSpeculative);
709 // Read uniq reg into ABI return value register (r0)
710 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
711 // Write uniq reg with value from ABI arg register (r16)
712 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
718 0x1b: decode PALMODE {
719 0: OpcdecFault::hw_st_quad();
720 1: decode HW_LDST_QUAD {
722 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
723 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
728 0x1f: decode PALMODE {
729 0: OpcdecFault::hw_st_cond();
731 1: decode HW_LDST_COND {
732 0: decode HW_LDST_QUAD {
733 0: hw_st({{ EA = (Rb + disp) & ~3; }},
734 {{ Mem.ul = Ra<31:0>; }}, L);
735 1: hw_st({{ EA = (Rb + disp) & ~7; }},
736 {{ Mem.uq = Ra.uq; }}, Q);
739 1: FailUnimpl::hw_st_cond();
744 0x19: decode PALMODE {
745 0: OpcdecFault::hw_mfpr();
748 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
749 IprToMiscRegIndex[ipr_index] : -1;
750 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
751 miscRegIndex >= NumInternalProcRegs)
752 fault = new UnimplementedOpcodeFault;
754 Ra = xc->readMiscRegWithEffect(miscRegIndex);
759 0x1d: decode PALMODE {
760 0: OpcdecFault::hw_mtpr();
763 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
764 IprToMiscRegIndex[ipr_index] : -1;
765 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
766 miscRegIndex >= NumInternalProcRegs)
767 fault = new UnimplementedOpcodeFault;
769 xc->setMiscRegWithEffect(miscRegIndex, Ra);
770 if (traceData) { traceData->setData(Ra); }
775 format BasicOperate {
776 0x1e: decode PALMODE {
777 0: OpcdecFault::hw_rei();
778 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
781 // M5 special opcodes use the reserved 0x01 opcode space
782 0x01: decode M5FUNC {
784 AlphaPseudo::arm(xc->tcBase());
785 }}, IsNonSpeculative);
787 AlphaPseudo::quiesce(xc->tcBase());
788 }}, IsNonSpeculative, IsQuiesce);
790 AlphaPseudo::quiesceNs(xc->tcBase(), R16);
791 }}, IsNonSpeculative, IsQuiesce);
792 0x03: quiesceCycles({{
793 AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
794 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
796 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
797 }}, IsNonSpeculative, IsUnverifiable);
799 AlphaPseudo::m5exit_old(xc->tcBase());
800 }}, No_OpClass, IsNonSpeculative);
802 AlphaPseudo::m5exit(xc->tcBase(), R16);
803 }}, No_OpClass, IsNonSpeculative);
805 AlphaPseudo::loadsymbol(xc->tcBase());
806 }}, No_OpClass, IsNonSpeculative);
807 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
809 AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
810 }}, IsNonSpeculative);
812 AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
813 }}, IsNonSpeculative);
814 0x42: dumpresetstats({{
815 AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
816 }}, IsNonSpeculative);
817 0x43: m5checkpoint({{
818 AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
819 }}, IsNonSpeculative);
821 R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
822 }}, IsNonSpeculative);
824 AlphaPseudo::debugbreak(xc->tcBase());
825 }}, IsNonSpeculative);
827 AlphaPseudo::switchcpu(xc->tcBase());
828 }}, IsNonSpeculative);
830 AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
831 }}, IsNonSpeculative);
833 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
834 }}, IsNonSpeculative);
836 AlphaPseudo::anBegin(xc->tcBase(), R16);
837 }}, IsNonSpeculative);
839 AlphaPseudo::anWait(xc->tcBase(), R16, R17);
840 }}, IsNonSpeculative);