src/arch/alpha/isa/fp.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Steve Reinhardt
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Floating-point instructions
  34 //
  35 //      Note that many FP-type instructions which do not support all the
  36 //      various rounding & trapping modes use the simpler format
  37 //      BasicOperateWithNopCheck.
  38 //
  39
  40 output exec {{
  41     /// Check "FP enabled" machine status bit.  Called when executing any FP
  42     /// instruction in full-system mode.
  43     /// @retval Full-system mode: NoFault if FP is enabled, FenFault
  44     /// if not.  Non-full-system mode: always returns NoFault.
  45     inline Fault checkFpEnableFault(ExecContext *xc)
  46     {
  47         Fault fault = NoFault;  // dummy... this ipr access should not fault
  48         if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
  49             fault = std::make_shared<FloatEnableFault>();
  50         }
  51         return fault;
  52     }
  53     inline Fault checkVectorEnableFault(ExecContext *xc) {
  54         return std::make_shared<VectorEnableFault>();
  55     }
  56 }};
  57
  58 output header {{
  59     /**
  60      * Base class for general floating-point instructions.  Includes
  61      * support for various Alpha rounding and trapping modes.  Only FP
  62      * instructions that require this support are derived from this
  63      * class; the rest derive directly from AlphaStaticInst.
  64      */
  65     class AlphaFP : public AlphaStaticInst
  66     {
  67       public:
  68         /// Alpha FP rounding modes.
  69         enum RoundingMode {
  70             Chopped = 0,        ///< round toward zero
  71             Minus_Infinity = 1, ///< round toward minus infinity
  72             Normal = 2,         ///< round to nearest (default)
  73             Dynamic = 3,        ///< use FPCR setting (in instruction)
  74             Plus_Infinity = 3   ///< round to plus inifinity (in FPCR)
  75         };
  76
  77         /// Alpha FP trapping modes.
  78         /// For instructions that produce integer results, the
  79         /// "Underflow Enable" modes really mean "Overflow Enable", and
  80         /// the assembly modifier is V rather than U.
  81         enum TrappingMode {
  82             /// default: nothing enabled
  83             Imprecise = 0,                 ///< no modifier
  84             /// underflow/overflow traps enabled, inexact disabled
  85             Underflow_Imprecise = 1,       ///< /U or /V
  86             Underflow_Precise = 5,         ///< /SU or /SV
  87             /// underflow/overflow and inexact traps enabled
  88             Underflow_Inexact_Precise = 7  ///< /SUI or /SVI
  89         };
  90
  91       protected:
  92         /// Map Alpha rounding mode to C99 constants from <fenv.h>.
  93         static const int alphaToC99RoundingMode[];
  94
  95         /// Map enum RoundingMode values to disassembly suffixes.
  96         static const char *roundingModeSuffix[];
  97         /// Map enum TrappingMode values to FP disassembly suffixes.
  98         static const char *fpTrappingModeSuffix[];
  99         /// Map enum TrappingMode values to integer disassembly suffixes.
 100         static const char *intTrappingModeSuffix[];
 101
 102         /// This instruction's rounding mode.
 103         RoundingMode roundingMode;
 104         /// This instruction's trapping mode.
 105         TrappingMode trappingMode;
 106
 107         /// Have we warned about this instruction's unsupported
 108         /// rounding mode (if applicable)?
 109         mutable bool warnedOnRounding;
 110
 111         /// Have we warned about this instruction's unsupported
 112         /// trapping mode (if applicable)?
 113         mutable bool warnedOnTrapping;
 114
 115         /// Constructor
 116         AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 117             : AlphaStaticInst(mnem, _machInst, __opClass),
 118               roundingMode((enum RoundingMode)FP_ROUNDMODE),
 119               trappingMode((enum TrappingMode)FP_TRAPMODE),
 120               warnedOnRounding(false),
 121               warnedOnTrapping(false)
 122         {
 123         }
 124
 125         int getC99RoundingMode(uint64_t fpcr_val) const;
 126
 127         // This differs from the AlphaStaticInst version only in
 128         // printing suffixes for non-default rounding & trapping modes.
 129         std::string generateDisassembly(
 130                 Addr pc, const SymbolTable *symtab) const override;
 131     };
 132
 133 }};
 134
 135
 136 output decoder {{
 137     int
 138     AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
 139     {
 140         if (roundingMode == Dynamic) {
 141             return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
 142         }
 143         else {
 144             return alphaToC99RoundingMode[roundingMode];
 145         }
 146     }
 147
 148     std::string
 149     AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 150     {
 151         std::string mnem_str(mnemonic);
 152
 153         std::string suffix("");
 154         suffix += ((_destRegIdx[0].isFloatReg())
 155                    ? fpTrappingModeSuffix[trappingMode]
 156                    : intTrappingModeSuffix[trappingMode]);
 157         suffix += roundingModeSuffix[roundingMode];
 158
 159         if (suffix != "") {
 160             mnem_str = csprintf("%s/%s", mnemonic, suffix);
 161         }
 162
 163         std::stringstream ss;
 164         ccprintf(ss, "%-10s ", mnem_str.c_str());
 165
 166         // just print the first two source regs... if there's
 167         // a third one, it's a read-modify-write dest (Rc),
 168         // e.g. for CMOVxx
 169         if (_numSrcRegs > 0) {
 170             printReg(ss, _srcRegIdx[0]);
 171         }
 172         if (_numSrcRegs > 1) {
 173             ss << ",";
 174             printReg(ss, _srcRegIdx[1]);
 175         }
 176
 177         // just print the first dest... if there's a second one,
 178         // it's generally implicit
 179         if (_numDestRegs > 0) {
 180             if (_numSrcRegs > 0)
 181                 ss << ",";
 182             printReg(ss, _destRegIdx[0]);
 183         }
 184
 185         return ss.str();
 186     }
 187
 188     const int AlphaFP::alphaToC99RoundingMode[] = {
 189         M5_FE_TOWARDZERO,       // Chopped
 190         M5_FE_DOWNWARD, // Minus_Infinity
 191         M5_FE_TONEAREST,        // Normal
 192         M5_FE_UPWARD    // Dynamic in inst, Plus_Infinity in FPCR
 193     };
 194
 195     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
 196     // mark invalid trapping modes, but don't fail on them, because
 197     // you could decode anything on a misspeculated path
 198     const char *AlphaFP::fpTrappingModeSuffix[] =
 199         { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
 200     const char *AlphaFP::intTrappingModeSuffix[] =
 201         { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
 202 }};
 203
 204 // FP instruction class execute method template.  Handles non-standard
 205 // rounding modes.
 206 def template FloatingPointExecute {{
 207     Fault %(class_name)s::execute(ExecContext *xc,
 208                                   Trace::InstRecord *traceData) const
 209     {
 210         if (trappingMode != Imprecise && !warnedOnTrapping) {
 211             warn("%s: non-standard trapping mode not supported",
 212                  generateDisassembly(0, NULL));
 213             warnedOnTrapping = true;
 214         }
 215
 216         Fault fault = NoFault;
 217
 218         %(fp_enable_check)s;
 219         %(op_decl)s;
 220         %(op_rd)s;
 221 #if USE_FENV
 222         if (roundingMode == Normal) {
 223             %(code)s;
 224         } else {
 225             m5_fesetround(getC99RoundingMode(
 226                            xc->readMiscReg(MISCREG_FPCR)));
 227             %(code)s;
 228             m5_fesetround(M5_FE_TONEAREST);
 229         }
 230 #else
 231         if (roundingMode != Normal && !warnedOnRounding) {
 232             warn("%s: non-standard rounding mode not supported",
 233                  generateDisassembly(0, NULL));
 234             warnedOnRounding = true;
 235         }
 236         %(code)s;
 237 #endif
 238
 239         if (fault == NoFault) {
 240             %(op_wb)s;
 241         }
 242
 243         return fault;
 244     }
 245 }};
 246
 247 // FP instruction class execute method template where no dynamic
 248 // rounding mode control is needed.  Like BasicExecute, but includes
 249 // check & warning for non-standard trapping mode.
 250 def template FPFixedRoundingExecute {{
 251     Fault %(class_name)s::execute(ExecContext *xc,
 252                                   Trace::InstRecord *traceData) const
 253     {
 254         if (trappingMode != Imprecise && !warnedOnTrapping) {
 255             warn("%s: non-standard trapping mode not supported",
 256                  generateDisassembly(0, NULL));
 257             warnedOnTrapping = true;
 258         }
 259
 260         Fault fault = NoFault;
 261
 262         %(fp_enable_check)s;
 263         %(op_decl)s;
 264         %(op_rd)s;
 265         %(code)s;
 266
 267         if (fault == NoFault) {
 268             %(op_wb)s;
 269         }
 270
 271         return fault;
 272     }
 273 }};
 274
 275 def template FloatingPointDecode {{
 276  {
 277      AlphaStaticInst *i = new %(class_name)s(machInst);
 278      if (FC == 31) {
 279          i = makeNop(i);
 280      }
 281      return i;
 282  }
 283 }};
 284
 285 // General format for floating-point operate instructions:
 286 // - Checks trapping and rounding mode flags.  Trapping modes
 287 //   currently unimplemented (will fail).
 288 // - Generates NOP if FC == 31.
 289 def format FloatingPointOperate(code, *opt_args) {{
 290     iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
 291     decode_block = FloatingPointDecode.subst(iop)
 292     header_output = BasicDeclare.subst(iop)
 293     decoder_output = BasicConstructor.subst(iop)
 294     exec_output = FloatingPointExecute.subst(iop)
 295 }};
 296
 297 // Special format for cvttq where rounding mode is pre-decoded
 298 def format FPFixedRounding(code, class_suffix, *opt_args) {{
 299     Name += class_suffix
 300     iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
 301     decode_block = FloatingPointDecode.subst(iop)
 302     header_output = BasicDeclare.subst(iop)
 303     decoder_output = BasicConstructor.subst(iop)
 304     exec_output = FPFixedRoundingExecute.subst(iop)
 305 }};
 306