src/arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Steve Reinhardt
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Alpha ISA description file.
  34 //
  35 ////////////////////////////////////////////////////////////////////
  36
  37
  38 ////////////////////////////////////////////////////////////////////
  39 //
  40 // Output include file directives.
  41 //
  42
  43 output header {{
  44 #include <sstream>
  45 #include <iostream>
  46 #include <iomanip>
  47
  48 #include "arch/alpha/faults.hh"
  49 #include "config/ss_compatible_fp.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "mem/request.hh"  // some constructors use MemReq flags
  52 #include "mem/packet.hh"
  53 }};
  54
  55 output decoder {{
  56 #include <cmath>
  57
  58 #include "arch/alpha/registers.hh"
  59 #include "arch/alpha/regredir.hh"
  60 #include "base/cprintf.hh"
  61 #include "base/fenv.hh"
  62 #include "base/loader/symtab.hh"
  63 #include "config/ss_compatible_fp.hh"
  64 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
  65 #include "mem/packet.hh"
  66
  67 using namespace AlphaISA;
  68 }};
  69
  70 output exec {{
  71 #include <math.h>
  72
  73 #include "arch/alpha/regredir.hh"
  74 #include "base/cp_annotate.hh"
  75 #include "sim/pseudo_inst.hh"
  76 #include "arch/alpha/registers.hh"
  77 #include "base/fenv.hh"
  78 #include "config/ss_compatible_fp.hh"
  79 #include "cpu/base.hh"
  80 #include "cpu/exetrace.hh"
  81 #include "mem/packet.hh"
  82 #include "mem/packet_access.hh"
  83 #include "sim/sim_exit.hh"
  84
  85 using namespace AlphaISA;
  86 }};
  87
  88 ////////////////////////////////////////////////////////////////////
  89 //
  90 // Namespace statement.  Everything below this line will be in the
  91 // AlphaISAInst namespace.
  92 //
  93
  94
  95 namespace AlphaISA;
  96
  97 ////////////////////////////////////////////////////////////////////
  98 //
  99 // Bitfield definitions.
 100 //
 101
 102 // Universal (format-independent) fields
 103 def bitfield PALMODE    <32:32>;
 104 def bitfield OPCODE     <31:26>;
 105 def bitfield RA         <25:21>;
 106 def bitfield RB         <20:16>;
 107
 108 // Memory format
 109 def signed bitfield MEMDISP <15: 0>; // displacement
 110 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
 111
 112 // Memory-format jumps
 113 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
 114 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
 115
 116 // Branch format
 117 def signed bitfield BRDISP <20: 0>; // displacement
 118
 119 // Integer operate format(s>;
 120 def bitfield INTIMM     <20:13>; // integer immediate (literal)
 121 def bitfield IMM        <12:12>; // immediate flag
 122 def bitfield INTFUNC    <11: 5>; // function code
 123 def bitfield RC         < 4: 0>; // dest reg
 124
 125 // Floating-point operate format
 126 def bitfield FA           <25:21>;
 127 def bitfield FB           <20:16>;
 128 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 129     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 130     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 131     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 132         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 133         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 134         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 135 def bitfield FC           < 4: 0>; // dest reg
 136
 137 // PALcode format
 138 def bitfield PALFUNC    <25: 0>; // function code
 139
 140 // EV5 PAL instructions:
 141 // HW_LD/HW_ST
 142 def bitfield HW_LDST_PHYS  <15>; // address is physical
 143 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 144 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 145 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 146 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 147 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 148 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 149 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 150
 151 // HW_REI
 152 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 153 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 154
 155 // HW_MTPR/MW_MFPR
 156 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 157
 158 // M5 instructions
 159 def bitfield M5FUNC <7:0>;
 160
 161 def operand_types {{
 162     'sb' : ('signed int', 8),
 163     'ub' : ('unsigned int', 8),
 164     'sw' : ('signed int', 16),
 165     'uw' : ('unsigned int', 16),
 166     'sl' : ('signed int', 32),
 167     'ul' : ('unsigned int', 32),
 168     'sq' : ('signed int', 64),
 169     'uq' : ('unsigned int', 64),
 170     'sf' : ('float', 32),
 171     'df' : ('float', 64)
 172 }};
 173
 174 def operands {{
 175     # Int regs default to unsigned, but code should not count on this.
 176     # For clarity, descriptions that depend on unsigned behavior should
 177     # explicitly specify '.uq'.
 178     'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
 179            'IsInteger', 1),
 180     'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
 181            'IsInteger', 2),
 182     'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
 183            'IsInteger', 3),
 184     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 185     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 186     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 187     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 188     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 189     'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
 190     'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
 191     'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
 192     # The next two are hacks for non-full-system call-pal emulation
 193     'R0':  ('IntReg', 'uq', '0', None, 1),
 194     'R16': ('IntReg', 'uq', '16', None, 1),
 195     'R17': ('IntReg', 'uq', '17', None, 1),
 196     'R18': ('IntReg', 'uq', '18', None, 1)
 197 }};
 198
 199 ////////////////////////////////////////////////////////////////////
 200 //
 201 // Basic instruction classes/templates/formats etc.
 202 //
 203
 204 output header {{
 205 // uncomment the following to get SimpleScalar-compatible disassembly
 206 // (useful for diffing output traces).
 207 // #define SS_COMPATIBLE_DISASSEMBLY
 208
 209     /**
 210      * Base class for all Alpha static instructions.
 211      */
 212     class AlphaStaticInst : public StaticInst
 213     {
 214       protected:
 215
 216         /// Make AlphaISA register dependence tags directly visible in
 217         /// this class and derived classes.  Maybe these should really
 218         /// live here and not in the AlphaISA namespace.
 219         enum DependenceTags {
 220             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 221         };
 222
 223         /// Constructor.
 224         AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
 225                         OpClass __opClass)
 226             : StaticInst(mnem, _machInst, __opClass)
 227         {
 228         }
 229
 230         /// Print a register name for disassembly given the unique
 231         /// dependence tag number (FP or int).
 232         void printReg(std::ostream &os, int reg) const;
 233
 234         std::string
 235         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 236     };
 237 }};
 238
 239 output decoder {{
 240     void
 241     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 242     {
 243         if (reg < FP_Base_DepTag) {
 244             ccprintf(os, "r%d", reg);
 245         }
 246         else {
 247             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 248         }
 249     }
 250
 251     std::string
 252     AlphaStaticInst::generateDisassembly(Addr pc,
 253                                          const SymbolTable *symtab) const
 254     {
 255         std::stringstream ss;
 256
 257         ccprintf(ss, "%-10s ", mnemonic);
 258
 259         // just print the first two source regs... if there's
 260         // a third one, it's a read-modify-write dest (Rc),
 261         // e.g. for CMOVxx
 262         if (_numSrcRegs > 0) {
 263             printReg(ss, _srcRegIdx[0]);
 264         }
 265         if (_numSrcRegs > 1) {
 266             ss << ",";
 267             printReg(ss, _srcRegIdx[1]);
 268         }
 269
 270         // just print the first dest... if there's a second one,
 271         // it's generally implicit
 272         if (_numDestRegs > 0) {
 273             if (_numSrcRegs > 0)
 274                 ss << ",";
 275             printReg(ss, _destRegIdx[0]);
 276         }
 277
 278         return ss.str();
 279     }
 280 }};
 281
 282 // Declarations for execute() methods.
 283 def template BasicExecDeclare {{
 284     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 285 }};
 286
 287 // Basic instruction class declaration template.
 288 def template BasicDeclare {{
 289     /**
 290      * Static instruction class for "%(mnemonic)s".
 291      */
 292     class %(class_name)s : public %(base_class)s
 293     {
 294       public:
 295         /// Constructor.
 296         %(class_name)s(ExtMachInst machInst);
 297
 298         %(BasicExecDeclare)s
 299     };
 300 }};
 301
 302 // Basic instruction class constructor template.
 303 def template BasicConstructor {{
 304     inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
 305          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 306     {
 307         %(constructor)s;
 308     }
 309 }};
 310
 311 // Basic instruction class execute method template.
 312 def template BasicExecute {{
 313     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 314                                   Trace::InstRecord *traceData) const
 315     {
 316         Fault fault = NoFault;
 317
 318         %(fp_enable_check)s;
 319         %(op_decl)s;
 320         %(op_rd)s;
 321         %(code)s;
 322
 323         if (fault == NoFault) {
 324             %(op_wb)s;
 325         }
 326
 327         return fault;
 328     }
 329 }};
 330
 331 // Basic decode template.
 332 def template BasicDecode {{
 333     return new %(class_name)s(machInst);
 334 }};
 335
 336 // Basic decode template, passing mnemonic in as string arg to constructor.
 337 def template BasicDecodeWithMnemonic {{
 338     return new %(class_name)s("%(mnemonic)s", machInst);
 339 }};
 340
 341 // The most basic instruction format... used only for a few misc. insts
 342 def format BasicOperate(code, *flags) {{
 343     iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
 344     header_output = BasicDeclare.subst(iop)
 345     decoder_output = BasicConstructor.subst(iop)
 346     decode_block = BasicDecode.subst(iop)
 347     exec_output = BasicExecute.subst(iop)
 348 }};
 349
 350
 351
 352 ////////////////////////////////////////////////////////////////////
 353 //
 354 // Nop
 355 //
 356
 357 output header {{
 358     /**
 359      * Static instruction class for no-ops.  This is a leaf class.
 360      */
 361     class Nop : public AlphaStaticInst
 362     {
 363         /// Disassembly of original instruction.
 364         const std::string originalDisassembly;
 365
 366       public:
 367         /// Constructor
 368         Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
 369             : AlphaStaticInst("nop", _machInst, No_OpClass),
 370               originalDisassembly(_originalDisassembly)
 371         {
 372             flags[IsNop] = true;
 373         }
 374
 375         ~Nop() { }
 376
 377         std::string
 378         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 379
 380         %(BasicExecDeclare)s
 381     };
 382
 383     /// Helper function for decoding nops.  Substitute Nop object
 384     /// for original inst passed in as arg (and delete latter).
 385     static inline
 386     AlphaStaticInst *
 387     makeNop(AlphaStaticInst *inst)
 388     {
 389         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 390         delete inst;
 391         return nop;
 392     }
 393 }};
 394
 395 output decoder {{
 396     std::string Nop::generateDisassembly(Addr pc,
 397                                          const SymbolTable *symtab) const
 398     {
 399 #ifdef SS_COMPATIBLE_DISASSEMBLY
 400         return originalDisassembly;
 401 #else
 402         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 403 #endif
 404     }
 405 }};
 406
 407 output exec {{
 408     Fault
 409     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 410     {
 411         return NoFault;
 412     }
 413 }};
 414
 415 // integer & FP operate instructions use Rc as dest, so check for
 416 // Rc == 31 to detect nops
 417 def template OperateNopCheckDecode {{
 418  {
 419      AlphaStaticInst *i = new %(class_name)s(machInst);
 420      if (RC == 31) {
 421          i = makeNop(i);
 422      }
 423      return i;
 424  }
 425 }};
 426
 427 // Like BasicOperate format, but generates NOP if RC/FC == 31
 428 def format BasicOperateWithNopCheck(code, *opt_args) {{
 429     iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
 430     header_output = BasicDeclare.subst(iop)
 431     decoder_output = BasicConstructor.subst(iop)
 432     decode_block = OperateNopCheckDecode.subst(iop)
 433     exec_output = BasicExecute.subst(iop)
 434 }};
 435
 436 // Integer instruction templates, formats, etc.
 437 ##include "int.isa"
 438
 439 // Floating-point instruction templates, formats, etc.
 440 ##include "fp.isa"
 441
 442 // Memory instruction templates, formats, etc.
 443 ##include "mem.isa"
 444
 445 // Branch/jump instruction templates, formats, etc.
 446 ##include "branch.isa"
 447
 448 // PAL instruction templates, formats, etc.
 449 ##include "pal.isa"
 450
 451 // Opcdec fault instruction templates, formats, etc.
 452 ##include "opcdec.isa"
 453
 454 // Unimplemented instruction templates, formats, etc.
 455 ##include "unimp.isa"
 456
 457 // Unknown instruction templates, formats, etc.
 458 ##include "unknown.isa"
 459
 460 // Execution utility functions
 461 ##include "util.isa"
 462
 463 // The actual decoder
 464 ##include "decoder.isa"