src/arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Steve Reinhardt
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Alpha ISA description file.
  34 //
  35 ////////////////////////////////////////////////////////////////////
  36
  37
  38 ////////////////////////////////////////////////////////////////////
  39 //
  40 // Output include file directives.
  41 //
  42
  43 output header {{
  44 #include <sstream>
  45 #include <iostream>
  46 #include <iomanip>
  47
  48 #include "arch/alpha/faults.hh"
  49 #include "config/ss_compatible_fp.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "mem/request.hh"  // some constructors use MemReq flags
  52 #include "mem/packet.hh"
  53 }};
  54
  55 output decoder {{
  56 #include <cmath>
  57
  58 #include "base/cprintf.hh"
  59 #include "base/fenv.hh"
  60 #include "base/loader/symtab.hh"
  61 #include "config/ss_compatible_fp.hh"
  62 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
  63 #include "mem/packet.hh"
  64
  65 using namespace AlphaISA;
  66 }};
  67
  68 output exec {{
  69 #include <math.h>
  70
  71 #include "sim/pseudo_inst.hh"
  72 #include "arch/alpha/ipr.hh"
  73 #include "base/fenv.hh"
  74 #include "config/ss_compatible_fp.hh"
  75 #include "cpu/base.hh"
  76 #include "cpu/exetrace.hh"
  77 #include "mem/packet.hh"
  78 #include "mem/packet_access.hh"
  79 #include "sim/sim_exit.hh"
  80
  81 using namespace AlphaISA;
  82 }};
  83
  84 ////////////////////////////////////////////////////////////////////
  85 //
  86 // Namespace statement.  Everything below this line will be in the
  87 // AlphaISAInst namespace.
  88 //
  89
  90
  91 namespace AlphaISA;
  92
  93 ////////////////////////////////////////////////////////////////////
  94 //
  95 // Bitfield definitions.
  96 //
  97
  98 // Universal (format-independent) fields
  99 def bitfield PALMODE    <32:32>;
 100 def bitfield OPCODE     <31:26>;
 101 def bitfield RA         <25:21>;
 102 def bitfield RB         <20:16>;
 103
 104 // Memory format
 105 def signed bitfield MEMDISP <15: 0>; // displacement
 106 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
 107
 108 // Memory-format jumps
 109 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
 110 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
 111
 112 // Branch format
 113 def signed bitfield BRDISP <20: 0>; // displacement
 114
 115 // Integer operate format(s>;
 116 def bitfield INTIMM     <20:13>; // integer immediate (literal)
 117 def bitfield IMM        <12:12>; // immediate flag
 118 def bitfield INTFUNC    <11: 5>; // function code
 119 def bitfield RC         < 4: 0>; // dest reg
 120
 121 // Floating-point operate format
 122 def bitfield FA           <25:21>;
 123 def bitfield FB           <20:16>;
 124 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 125     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 126     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 127     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 128         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 129         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 130         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 131 def bitfield FC           < 4: 0>; // dest reg
 132
 133 // PALcode format
 134 def bitfield PALFUNC    <25: 0>; // function code
 135
 136 // EV5 PAL instructions:
 137 // HW_LD/HW_ST
 138 def bitfield HW_LDST_PHYS  <15>; // address is physical
 139 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 140 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 141 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 142 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 143 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 144 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 145 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 146
 147 // HW_REI
 148 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 149 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 150
 151 // HW_MTPR/MW_MFPR
 152 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 153
 154 // M5 instructions
 155 def bitfield M5FUNC <7:0>;
 156
 157 def operand_types {{
 158     'sb' : ('signed int', 8),
 159     'ub' : ('unsigned int', 8),
 160     'sw' : ('signed int', 16),
 161     'uw' : ('unsigned int', 16),
 162     'sl' : ('signed int', 32),
 163     'ul' : ('unsigned int', 32),
 164     'sq' : ('signed int', 64),
 165     'uq' : ('unsigned int', 64),
 166     'sf' : ('float', 32),
 167     'df' : ('float', 64)
 168 }};
 169
 170 def operands {{
 171     # Int regs default to unsigned, but code should not count on this.
 172     # For clarity, descriptions that depend on unsigned behavior should
 173     # explicitly specify '.uq'.
 174     'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
 175            'IsInteger', 1),
 176     'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
 177            'IsInteger', 2),
 178     'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
 179            'IsInteger', 3),
 180     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 181     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 182     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 183     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 184     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 185     'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
 186     'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
 187     'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
 188     # The next two are hacks for non-full-system call-pal emulation
 189     'R0':  ('IntReg', 'uq', '0', None, 1),
 190     'R16': ('IntReg', 'uq', '16', None, 1),
 191     'R17': ('IntReg', 'uq', '17', None, 1),
 192     'R18': ('IntReg', 'uq', '18', None, 1)
 193 }};
 194
 195 ////////////////////////////////////////////////////////////////////
 196 //
 197 // Basic instruction classes/templates/formats etc.
 198 //
 199
 200 output header {{
 201 // uncomment the following to get SimpleScalar-compatible disassembly
 202 // (useful for diffing output traces).
 203 // #define SS_COMPATIBLE_DISASSEMBLY
 204
 205     /**
 206      * Base class for all Alpha static instructions.
 207      */
 208     class AlphaStaticInst : public StaticInst
 209     {
 210       protected:
 211
 212         /// Make AlphaISA register dependence tags directly visible in
 213         /// this class and derived classes.  Maybe these should really
 214         /// live here and not in the AlphaISA namespace.
 215         enum DependenceTags {
 216             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 217         };
 218
 219         /// Constructor.
 220         AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
 221                         OpClass __opClass)
 222             : StaticInst(mnem, _machInst, __opClass)
 223         {
 224         }
 225
 226         /// Print a register name for disassembly given the unique
 227         /// dependence tag number (FP or int).
 228         void printReg(std::ostream &os, int reg) const;
 229
 230         std::string
 231         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 232     };
 233 }};
 234
 235 output decoder {{
 236     void
 237     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 238     {
 239         if (reg < FP_Base_DepTag) {
 240             ccprintf(os, "r%d", reg);
 241         }
 242         else {
 243             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 244         }
 245     }
 246
 247     std::string
 248     AlphaStaticInst::generateDisassembly(Addr pc,
 249                                          const SymbolTable *symtab) const
 250     {
 251         std::stringstream ss;
 252
 253         ccprintf(ss, "%-10s ", mnemonic);
 254
 255         // just print the first two source regs... if there's
 256         // a third one, it's a read-modify-write dest (Rc),
 257         // e.g. for CMOVxx
 258         if (_numSrcRegs > 0) {
 259             printReg(ss, _srcRegIdx[0]);
 260         }
 261         if (_numSrcRegs > 1) {
 262             ss << ",";
 263             printReg(ss, _srcRegIdx[1]);
 264         }
 265
 266         // just print the first dest... if there's a second one,
 267         // it's generally implicit
 268         if (_numDestRegs > 0) {
 269             if (_numSrcRegs > 0)
 270                 ss << ",";
 271             printReg(ss, _destRegIdx[0]);
 272         }
 273
 274         return ss.str();
 275     }
 276 }};
 277
 278 // Declarations for execute() methods.
 279 def template BasicExecDeclare {{
 280     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 281 }};
 282
 283 // Basic instruction class declaration template.
 284 def template BasicDeclare {{
 285     /**
 286      * Static instruction class for "%(mnemonic)s".
 287      */
 288     class %(class_name)s : public %(base_class)s
 289     {
 290       public:
 291         /// Constructor.
 292         %(class_name)s(ExtMachInst machInst);
 293
 294         %(BasicExecDeclare)s
 295     };
 296 }};
 297
 298 // Basic instruction class constructor template.
 299 def template BasicConstructor {{
 300     inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
 301          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 302     {
 303         %(constructor)s;
 304     }
 305 }};
 306
 307 // Basic instruction class execute method template.
 308 def template BasicExecute {{
 309     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 310                                   Trace::InstRecord *traceData) const
 311     {
 312         Fault fault = NoFault;
 313
 314         %(fp_enable_check)s;
 315         %(op_decl)s;
 316         %(op_rd)s;
 317         %(code)s;
 318
 319         if (fault == NoFault) {
 320             %(op_wb)s;
 321         }
 322
 323         return fault;
 324     }
 325 }};
 326
 327 // Basic decode template.
 328 def template BasicDecode {{
 329     return new %(class_name)s(machInst);
 330 }};
 331
 332 // Basic decode template, passing mnemonic in as string arg to constructor.
 333 def template BasicDecodeWithMnemonic {{
 334     return new %(class_name)s("%(mnemonic)s", machInst);
 335 }};
 336
 337 // The most basic instruction format... used only for a few misc. insts
 338 def format BasicOperate(code, *flags) {{
 339     iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
 340     header_output = BasicDeclare.subst(iop)
 341     decoder_output = BasicConstructor.subst(iop)
 342     decode_block = BasicDecode.subst(iop)
 343     exec_output = BasicExecute.subst(iop)
 344 }};
 345
 346
 347
 348 ////////////////////////////////////////////////////////////////////
 349 //
 350 // Nop
 351 //
 352
 353 output header {{
 354     /**
 355      * Static instruction class for no-ops.  This is a leaf class.
 356      */
 357     class Nop : public AlphaStaticInst
 358     {
 359         /// Disassembly of original instruction.
 360         const std::string originalDisassembly;
 361
 362       public:
 363         /// Constructor
 364         Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
 365             : AlphaStaticInst("nop", _machInst, No_OpClass),
 366               originalDisassembly(_originalDisassembly)
 367         {
 368             flags[IsNop] = true;
 369         }
 370
 371         ~Nop() { }
 372
 373         std::string
 374         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 375
 376         %(BasicExecDeclare)s
 377     };
 378
 379     /// Helper function for decoding nops.  Substitute Nop object
 380     /// for original inst passed in as arg (and delete latter).
 381     static inline
 382     AlphaStaticInst *
 383     makeNop(AlphaStaticInst *inst)
 384     {
 385         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 386         delete inst;
 387         return nop;
 388     }
 389 }};
 390
 391 output decoder {{
 392     std::string Nop::generateDisassembly(Addr pc,
 393                                          const SymbolTable *symtab) const
 394     {
 395 #ifdef SS_COMPATIBLE_DISASSEMBLY
 396         return originalDisassembly;
 397 #else
 398         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 399 #endif
 400     }
 401 }};
 402
 403 output exec {{
 404     Fault
 405     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 406     {
 407         return NoFault;
 408     }
 409 }};
 410
 411 // integer & FP operate instructions use Rc as dest, so check for
 412 // Rc == 31 to detect nops
 413 def template OperateNopCheckDecode {{
 414  {
 415      AlphaStaticInst *i = new %(class_name)s(machInst);
 416      if (RC == 31) {
 417          i = makeNop(i);
 418      }
 419      return i;
 420  }
 421 }};
 422
 423 // Like BasicOperate format, but generates NOP if RC/FC == 31
 424 def format BasicOperateWithNopCheck(code, *opt_args) {{
 425     iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
 426     header_output = BasicDeclare.subst(iop)
 427     decoder_output = BasicConstructor.subst(iop)
 428     decode_block = OperateNopCheckDecode.subst(iop)
 429     exec_output = BasicExecute.subst(iop)
 430 }};
 431
 432 // Integer instruction templates, formats, etc.
 433 ##include "int.isa"
 434
 435 // Floating-point instruction templates, formats, etc.
 436 ##include "fp.isa"
 437
 438 // Memory instruction templates, formats, etc.
 439 ##include "mem.isa"
 440
 441 // Branch/jump instruction templates, formats, etc.
 442 ##include "branch.isa"
 443
 444 // PAL instruction templates, formats, etc.
 445 ##include "pal.isa"
 446
 447 // Opcdec fault instruction templates, formats, etc.
 448 ##include "opcdec.isa"
 449
 450 // Unimplemented instruction templates, formats, etc.
 451 ##include "unimp.isa"
 452
 453 // Unknown instruction templates, formats, etc.
 454 ##include "unknown.isa"
 455
 456 // Execution utility functions
 457 ##include "util.isa"
 458
 459 // The actual decoder
 460 ##include "decoder.isa"