3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
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15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
32 ////////////////////////////////////////////////////////////////////
34 // Memory-format instructions: LoadAddress, Load, Store
39 * Base class for general Alpha memory-format instructions.
41 class Memory : public AlphaStaticInst
45 /// Memory request flags. See mem_req_base.hh.
46 Request::Flags memAccessFlags;
49 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
50 : AlphaStaticInst(mnem, _machInst, __opClass)
54 std::string generateDisassembly(
55 Addr pc, const SymbolTable *symtab) const override;
59 * Base class for memory-format instructions using a 32-bit
60 * displacement (i.e. most of them).
62 class MemoryDisp32 : public Memory
65 /// Displacement for EA calculation (signed).
69 MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass),
78 * Base class for a few miscellaneous memory-format insts
79 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
80 * None of these instructions has a destination register either.
82 class MemoryNoDisp : public Memory
86 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
87 : Memory(mnem, _machInst, __opClass)
91 std::string generateDisassembly(
92 Addr pc, const SymbolTable *symtab) const override;
99 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
101 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
102 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
106 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
108 return csprintf("%-10s (r%d)", mnemonic, RB);
112 def format LoadAddress(code) {{
113 iop = InstObjParams(name, Name, 'MemoryDisp32', code)
114 header_output = BasicDeclare.subst(iop)
115 decoder_output = BasicConstructor.subst(iop)
116 decode_block = BasicDecode.subst(iop)
117 exec_output = BasicExecute.subst(iop)
121 def template LoadStoreDeclare {{
123 * Static instruction class for "%(mnemonic)s".
125 class %(class_name)s : public %(base_class)s
130 %(class_name)s(ExtMachInst machInst);
132 Fault execute(ExecContext *, Trace::InstRecord *) const override;
133 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
134 Fault completeAcc(PacketPtr, ExecContext *,
135 Trace::InstRecord *) const override;
139 def template LoadStoreConstructor {{
140 %(class_name)s::%(class_name)s(ExtMachInst machInst)
141 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
148 def template LoadExecute {{
149 Fault %(class_name)s::execute(ExecContext *xc,
150 Trace::InstRecord *traceData) const
153 Fault fault = NoFault;
160 if (fault == NoFault) {
161 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
165 if (fault == NoFault) {
174 def template LoadInitiateAcc {{
175 Fault %(class_name)s::initiateAcc(ExecContext *xc,
176 Trace::InstRecord *traceData) const
179 Fault fault = NoFault;
186 if (fault == NoFault) {
187 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
195 def template LoadCompleteAcc {{
196 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
197 Trace::InstRecord *traceData) const
199 Fault fault = NoFault;
204 getMem(pkt, Mem, traceData);
206 if (fault == NoFault) {
210 if (fault == NoFault) {
219 def template StoreExecute {{
220 Fault %(class_name)s::execute(ExecContext *xc,
221 Trace::InstRecord *traceData) const
224 Fault fault = NoFault;
231 if (fault == NoFault) {
235 if (fault == NoFault) {
236 fault = writeMemAtomic(xc, traceData, Mem, EA,
237 memAccessFlags, NULL);
240 if (fault == NoFault) {
244 if (fault == NoFault) {
252 def template StoreCondExecute {{
253 Fault %(class_name)s::execute(ExecContext *xc,
254 Trace::InstRecord *traceData) const
257 Fault fault = NoFault;
258 uint64_t write_result = 0;
265 if (fault == NoFault) {
269 if (fault == NoFault) {
270 fault = writeMemAtomic(xc, traceData, Mem, EA,
271 memAccessFlags, &write_result);
274 if (fault == NoFault) {
278 if (fault == NoFault) {
286 def template StoreInitiateAcc {{
287 Fault %(class_name)s::initiateAcc(ExecContext *xc,
288 Trace::InstRecord *traceData) const
291 Fault fault = NoFault;
298 if (fault == NoFault) {
302 if (fault == NoFault) {
303 fault = writeMemTiming(xc, traceData, Mem, EA,
304 memAccessFlags, NULL);
312 def template StoreCompleteAcc {{
313 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
314 Trace::InstRecord *traceData) const
321 def template StoreCondCompleteAcc {{
322 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
323 Trace::InstRecord *traceData) const
325 Fault fault = NoFault;
330 uint64_t write_result = pkt->req->getExtraData();
332 if (fault == NoFault) {
336 if (fault == NoFault) {
345 def template MiscExecute {{
346 Fault %(class_name)s::execute(ExecContext *xc,
347 Trace::InstRecord *traceData) const
350 Fault fault = NoFault;
357 warn_once("Prefetch instructions in Alpha do not do anything\n");
358 if (fault == NoFault) {
366 // Prefetches in Alpha don't actually do anything
367 // They just build an effective address and complete
368 def template MiscInitiateAcc {{
369 Fault %(class_name)s::initiateAcc(ExecContext *xc,
370 Trace::InstRecord *traceData) const
372 warn("initiateAcc undefined: Misc instruction does not support split "
379 def template MiscCompleteAcc {{
380 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
381 Trace::InstRecord *traceData) const
383 warn("completeAcc undefined: Misc instruction does not support split "
391 // load instructions use Ra as dest, so check for
392 // Ra == 31 to detect nops
393 def template LoadNopCheckDecode {{
395 AlphaStaticInst *i = new %(class_name)s(machInst);
404 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
405 def template LoadPrefetchCheckDecode {{
408 return new %(class_name)s(machInst);
411 return new %(class_name)sPrefetch(machInst);
418 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
419 postacc_code = '', base_class = 'MemoryDisp32',
420 decode_template = BasicDecode, exec_template_base = ''):
421 # Make sure flags are in lists (convert to lists if not).
422 mem_flags = makeList(mem_flags)
423 inst_flags = makeList(inst_flags)
425 iop = InstObjParams(name, Name, base_class,
426 { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
430 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
431 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
436 # The InitiateAcc template is the same for StoreCond templates as the
437 # corresponding Store template..
438 StoreCondInitiateAcc = StoreInitiateAcc
440 fullExecTemplate = eval(exec_template_base + 'Execute')
441 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
442 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
444 # (header_output, decoder_output, decode_block, exec_output)
445 return (LoadStoreDeclare.subst(iop),
446 LoadStoreConstructor.subst(iop),
447 decode_template.subst(iop),
448 fullExecTemplate.subst(iop)
449 + initiateAccTemplate.subst(iop)
450 + completeAccTemplate.subst(iop))
453 def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
454 mem_flags = [], inst_flags = []) {{
455 (header_output, decoder_output, decode_block, exec_output) = \
456 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
457 decode_template = LoadNopCheckDecode,
458 exec_template_base = 'Load')
462 // Note that the flags passed in apply only to the prefetch version
463 def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
464 mem_flags = [], pf_flags = [], inst_flags = []) {{
465 # declare the load instruction object and generate the decode block
466 (header_output, decoder_output, decode_block, exec_output) = \
467 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
468 decode_template = LoadPrefetchCheckDecode,
469 exec_template_base = 'Load')
471 # Declare the prefetch instruction object.
473 # Make sure flag args are lists so we can mess with them.
474 mem_flags = makeList(mem_flags)
475 pf_flags = makeList(pf_flags)
476 inst_flags = makeList(inst_flags)
478 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
479 pf_inst_flags = inst_flags
481 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
482 LoadStoreBase(name, Name + 'Prefetch', ea_code, ';',
483 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
485 header_output += pf_header_output
486 decoder_output += pf_decoder_output
487 exec_output += pf_exec_output
491 def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
492 mem_flags = [], inst_flags = []) {{
493 (header_output, decoder_output, decode_block, exec_output) = \
494 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
495 exec_template_base = 'Store')
499 def format StoreCond(memacc_code, postacc_code,
500 ea_code = {{ EA = Rb + disp; }},
501 mem_flags = [], inst_flags = []) {{
502 (header_output, decoder_output, decode_block, exec_output) = \
503 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
504 postacc_code, exec_template_base = 'StoreCond')
508 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
509 def format MiscPrefetch(ea_code, memacc_code,
510 mem_flags = [], inst_flags = []) {{
511 (header_output, decoder_output, decode_block, exec_output) = \
512 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
513 base_class = 'MemoryNoDisp', exec_template_base = 'Misc')