3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
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7 // modification, are permitted provided that the following conditions are
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11 // notice, this list of conditions and the following disclaimer in the
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14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
32 ////////////////////////////////////////////////////////////////////
34 // Memory-format instructions: LoadAddress, Load, Store
39 * Base class for general Alpha memory-format instructions.
41 class Memory : public AlphaStaticInst
45 /// Memory request flags. See mem_req_base.hh.
46 Request::Flags memAccessFlags;
49 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
50 : AlphaStaticInst(mnem, _machInst, __opClass)
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59 * Base class for memory-format instructions using a 32-bit
60 * displacement (i.e. most of them).
62 class MemoryDisp32 : public Memory
65 /// Displacement for EA calculation (signed).
69 MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass),
78 * Base class for a few miscellaneous memory-format insts
79 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
80 * None of these instructions has a destination register either.
82 class MemoryNoDisp : public Memory
86 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
87 : Memory(mnem, _machInst, __opClass)
92 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
99 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
101 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
102 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
106 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
108 return csprintf("%-10s (r%d)", mnemonic, RB);
112 def format LoadAddress(code) {{
113 iop = InstObjParams(name, Name, 'MemoryDisp32', code)
114 header_output = BasicDeclare.subst(iop)
115 decoder_output = BasicConstructor.subst(iop)
116 decode_block = BasicDecode.subst(iop)
117 exec_output = BasicExecute.subst(iop)
121 def template LoadStoreDeclare {{
123 * Static instruction class for "%(mnemonic)s".
125 class %(class_name)s : public %(base_class)s
130 %(class_name)s(ExtMachInst machInst);
136 %(InitiateAccDeclare)s
138 %(CompleteAccDeclare)s
143 def template EACompDeclare {{
144 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
147 def template InitiateAccDeclare {{
148 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
152 def template CompleteAccDeclare {{
153 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
154 Trace::InstRecord *) const;
157 def template LoadStoreConstructor {{
158 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
159 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
165 def template EACompExecute {{
166 Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
167 Trace::InstRecord *traceData) const
170 Fault fault = NoFault;
177 if (fault == NoFault) {
187 def template LoadExecute {{
188 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
189 Trace::InstRecord *traceData) const
192 Fault fault = NoFault;
199 if (fault == NoFault) {
200 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
204 if (fault == NoFault) {
213 def template LoadInitiateAcc {{
214 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
215 Trace::InstRecord *traceData) const
218 Fault fault = NoFault;
225 if (fault == NoFault) {
226 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
234 def template LoadCompleteAcc {{
235 Fault %(class_name)s::completeAcc(PacketPtr pkt,
236 %(CPU_exec_context)s *xc,
237 Trace::InstRecord *traceData) const
239 Fault fault = NoFault;
244 Mem = pkt->get<typeof(Mem)>();
246 if (fault == NoFault) {
250 if (fault == NoFault) {
259 def template StoreExecute {{
260 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
261 Trace::InstRecord *traceData) const
264 Fault fault = NoFault;
271 if (fault == NoFault) {
275 if (fault == NoFault) {
276 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
277 memAccessFlags, NULL);
280 if (fault == NoFault) {
284 if (fault == NoFault) {
292 def template StoreCondExecute {{
293 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
294 Trace::InstRecord *traceData) const
297 Fault fault = NoFault;
298 uint64_t write_result = 0;
305 if (fault == NoFault) {
309 if (fault == NoFault) {
310 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
311 memAccessFlags, &write_result);
314 if (fault == NoFault) {
318 if (fault == NoFault) {
326 def template StoreInitiateAcc {{
327 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
328 Trace::InstRecord *traceData) const
331 Fault fault = NoFault;
338 if (fault == NoFault) {
342 if (fault == NoFault) {
343 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
344 memAccessFlags, NULL);
352 def template StoreCompleteAcc {{
353 Fault %(class_name)s::completeAcc(PacketPtr pkt,
354 %(CPU_exec_context)s *xc,
355 Trace::InstRecord *traceData) const
357 Fault fault = NoFault;
362 if (fault == NoFault) {
366 if (fault == NoFault) {
375 def template StoreCondCompleteAcc {{
376 Fault %(class_name)s::completeAcc(PacketPtr pkt,
377 %(CPU_exec_context)s *xc,
378 Trace::InstRecord *traceData) const
380 Fault fault = NoFault;
385 uint64_t write_result = pkt->req->getExtraData();
387 if (fault == NoFault) {
391 if (fault == NoFault) {
400 def template MiscExecute {{
401 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
402 Trace::InstRecord *traceData) const
405 Fault fault = NoFault;
412 if (fault == NoFault) {
420 def template MiscInitiateAcc {{
421 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
422 Trace::InstRecord *traceData) const
424 warn("initiateAcc undefined: Misc instruction does not support split "
431 def template MiscCompleteAcc {{
432 Fault %(class_name)s::completeAcc(PacketPtr pkt,
433 %(CPU_exec_context)s *xc,
434 Trace::InstRecord *traceData) const
436 warn("completeAcc undefined: Misc instruction does not support split "
444 // load instructions use Ra as dest, so check for
445 // Ra == 31 to detect nops
446 def template LoadNopCheckDecode {{
448 AlphaStaticInst *i = new %(class_name)s(machInst);
457 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
458 def template LoadPrefetchCheckDecode {{
461 return new %(class_name)s(machInst);
464 return new %(class_name)sPrefetch(machInst);
471 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
472 postacc_code = '', base_class = 'MemoryDisp32',
473 decode_template = BasicDecode, exec_template_base = ''):
474 # Make sure flags are in lists (convert to lists if not).
475 mem_flags = makeList(mem_flags)
476 inst_flags = makeList(inst_flags)
478 # Some CPU models execute the memory operation as an atomic unit,
479 # while others want to separate them into an effective address
480 # computation and a memory access operation. As a result, we need
481 # to generate three StaticInst objects. Note that the latter two
482 # are nested inside the larger "atomic" one.
484 # Generate InstObjParams for each of the three objects. Note that
485 # they differ only in the set of code objects contained (which in
486 # turn affects the object's overall operand list).
487 iop = InstObjParams(name, Name, base_class,
488 { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
490 memacc_iop = InstObjParams(name, Name, base_class,
491 { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
495 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
496 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
498 memacc_iop.constructor += s
502 # The InitiateAcc template is the same for StoreCond templates as the
503 # corresponding Store template..
504 StoreCondInitiateAcc = StoreInitiateAcc
506 fullExecTemplate = eval(exec_template_base + 'Execute')
507 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
508 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
510 # (header_output, decoder_output, decode_block, exec_output)
511 return (LoadStoreDeclare.subst(iop),
512 LoadStoreConstructor.subst(iop),
513 decode_template.subst(iop),
514 fullExecTemplate.subst(iop)
515 + EACompExecute.subst(iop)
516 + initiateAccTemplate.subst(iop)
517 + completeAccTemplate.subst(iop))
520 def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
521 mem_flags = [], inst_flags = []) {{
522 (header_output, decoder_output, decode_block, exec_output) = \
523 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
524 decode_template = LoadNopCheckDecode,
525 exec_template_base = 'Load')
529 // Note that the flags passed in apply only to the prefetch version
530 def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
531 mem_flags = [], pf_flags = [], inst_flags = []) {{
532 # declare the load instruction object and generate the decode block
533 (header_output, decoder_output, decode_block, exec_output) = \
534 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
535 decode_template = LoadPrefetchCheckDecode,
536 exec_template_base = 'Load')
538 # Declare the prefetch instruction object.
540 # Make sure flag args are lists so we can mess with them.
541 mem_flags = makeList(mem_flags)
542 pf_flags = makeList(pf_flags)
543 inst_flags = makeList(inst_flags)
545 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
546 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
547 'IsDataPrefetch', 'MemReadOp']
549 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
550 LoadStoreBase(name, Name + 'Prefetch', ea_code,
551 'xc->prefetch(EA, memAccessFlags);',
552 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
554 header_output += pf_header_output
555 decoder_output += pf_decoder_output
556 exec_output += pf_exec_output
560 def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
561 mem_flags = [], inst_flags = []) {{
562 (header_output, decoder_output, decode_block, exec_output) = \
563 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
564 exec_template_base = 'Store')
568 def format StoreCond(memacc_code, postacc_code,
569 ea_code = {{ EA = Rb + disp; }},
570 mem_flags = [], inst_flags = []) {{
571 (header_output, decoder_output, decode_block, exec_output) = \
572 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
573 postacc_code, exec_template_base = 'StoreCond')
577 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
578 def format MiscPrefetch(ea_code, memacc_code,
579 mem_flags = [], inst_flags = []) {{
580 (header_output, decoder_output, decode_block, exec_output) = \
581 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
582 base_class = 'MemoryNoDisp', exec_template_base = 'Misc')