3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
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29 // Authors: Steve Reinhardt
31 ////////////////////////////////////////////////////////////////////
33 // PAL calls & PAL-specific instructions
38 * Base class for emulated call_pal calls (used only in
39 * non-full-system mode).
41 class EmulatedCallPal : public AlphaStaticInst
46 EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
48 : AlphaStaticInst(mnem, _machInst, __opClass)
52 std::string generateDisassembly(
53 Addr pc, const SymbolTable *symtab) const override;
59 EmulatedCallPal::generateDisassembly(Addr pc,
60 const SymbolTable *symtab) const
62 #ifdef SS_COMPATIBLE_DISASSEMBLY
63 return csprintf("%s %s", "call_pal", mnemonic);
65 return csprintf("%-10s %s", "call_pal", mnemonic);
70 def format EmulatedCallPal(code, *flags) {{
71 iop = InstObjParams(name, Name, 'EmulatedCallPal', code, flags)
72 header_output = BasicDeclare.subst(iop)
73 decoder_output = BasicConstructor.subst(iop)
74 decode_block = BasicDecode.subst(iop)
75 exec_output = BasicExecute.subst(iop)
80 * Base class for full-system-mode call_pal instructions.
81 * Probably could turn this into a leaf class and get rid of the
84 class CallPalBase : public AlphaStaticInst
87 int palFunc; ///< Function code part of instruction
88 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
89 bool palValid; ///< is the function code valid?
90 bool palPriv; ///< is this call privileged?
93 CallPalBase(const char *mnem, ExtMachInst _machInst,
96 std::string generateDisassembly(
97 Addr pc, const SymbolTable *symtab) const override;
103 CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
105 : AlphaStaticInst(mnem, _machInst, __opClass),
108 // From the 21164 HRM (paraphrased):
109 // Bit 7 of the function code (mask 0x80) indicates
110 // whether the call is privileged (bit 7 == 0) or
111 // unprivileged (bit 7 == 1). The privileged call table
112 // starts at 0x2000, the unprivielged call table starts at
113 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
115 const int palPrivMask = 0x80;
116 const int palOffsetMask = 0x3f;
118 // Pal call is invalid unless all other bits are 0
119 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
120 palPriv = ((machInst & palPrivMask) == 0);
121 int shortPalFunc = (machInst & palOffsetMask);
122 // Add 1 to base to set pal-mode bit
123 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
127 CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
129 return csprintf("%-10s %#x", "call_pal", palFunc);
133 def format CallPal(code, *flags) {{
134 iop = InstObjParams(name, Name, 'CallPalBase', code, flags)
135 header_output = BasicDeclare.subst(iop)
136 decoder_output = BasicConstructor.subst(iop)
137 decode_block = BasicDecode.subst(iop)
138 exec_output = BasicExecute.subst(iop)
141 ////////////////////////////////////////////////////////////////////
148 * Base class for hw_ld and hw_st.
150 class HwLoadStore : public Memory
154 /// Displacement for EA calculation (signed).
158 HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass);
160 std::string generateDisassembly(
161 Addr pc, const SymbolTable *symtab) const override;
168 HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
170 : Memory(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
172 memAccessFlags.clear();
173 if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
174 if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE);
175 if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
176 if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
180 HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
182 #ifdef SS_COMPATIBLE_DISASSEMBLY
183 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
185 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
186 const char *lock_str =
187 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
189 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
190 mnemonic, RA, disp, RB,
191 HW_LDST_PHYS ? ",PHYS" : "",
192 HW_LDST_ALT ? ",ALT" : "",
193 HW_LDST_QUAD ? ",QUAD" : "",
194 HW_LDST_VPTE ? ",VPTE" : "",
200 def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
201 (header_output, decoder_output, decode_block, exec_output) = \
202 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
203 mem_flags = [], inst_flags = flags,
204 base_class = 'HwLoadStore', exec_template_base = 'Load')
208 def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
209 (header_output, decoder_output, decode_block, exec_output) = \
210 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
211 mem_flags = [], inst_flags = flags,
212 base_class = 'HwLoadStore', exec_template_base = 'Store')
216 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
218 (header_output, decoder_output, decode_block, exec_output) = \
219 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
220 postacc_code, mem_flags = [], inst_flags = flags,
221 base_class = 'HwLoadStore')
227 * Base class for hw_mfpr and hw_mtpr.
229 class HwMoveIPR : public AlphaStaticInst
232 /// Index of internal processor register.
236 HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
237 : AlphaStaticInst(mnem, _machInst, __opClass),
238 ipr_index(HW_IPR_IDX)
242 std::string generateDisassembly(
243 Addr pc, const SymbolTable *symtab) const override;
249 HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
251 if (_numSrcRegs > 0) {
253 return csprintf("%-10s r%d,IPR(%#x)",
254 mnemonic, RA, ipr_index);
258 return csprintf("%-10s IPR(%#x),r%d",
259 mnemonic, ipr_index, RA);
264 def format HwMoveIPR(code, *flags) {{
265 all_flags = ['IprAccessOp']
267 iop = InstObjParams(name, Name, 'HwMoveIPR', code, all_flags)
268 header_output = BasicDeclare.subst(iop)
269 decoder_output = BasicConstructor.subst(iop)
270 decode_block = BasicDecode.subst(iop)
271 exec_output = BasicExecute.subst(iop)