X86: Compute PCI config addresses correctly.
[gem5.git] / src / arch / alpha / isa / unimp.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 //
29 // Authors: Steve Reinhardt
30
31 ////////////////////////////////////////////////////////////////////
32 //
33 // Unimplemented instructions
34 //
35
36 output header {{
37 /**
38 * Static instruction class for unimplemented instructions that
39 * cause simulator termination. Note that these are recognized
40 * (legal) instructions that the simulator does not support; the
41 * 'Unknown' class is used for unrecognized/illegal instructions.
42 * This is a leaf class.
43 */
44 class FailUnimplemented : public AlphaStaticInst
45 {
46 public:
47 /// Constructor
48 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
49 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
50 {
51 // don't call execute() (which panics) if we're on a
52 // speculative path
53 flags[IsNonSpeculative] = true;
54 }
55
56 %(BasicExecDeclare)s
57
58 std::string
59 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
60 };
61
62 /**
63 * Base class for unimplemented instructions that cause a warning
64 * to be printed (but do not terminate simulation). This
65 * implementation is a little screwy in that it will print a
66 * warning for each instance of a particular unimplemented machine
67 * instruction, not just for each unimplemented opcode. Should
68 * probably make the 'warned' flag a static member of the derived
69 * class.
70 */
71 class WarnUnimplemented : public AlphaStaticInst
72 {
73 private:
74 /// Have we warned on this instruction yet?
75 mutable bool warned;
76
77 public:
78 /// Constructor
79 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
80 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
81 {
82 // don't call execute() (which panics) if we're on a
83 // speculative path
84 flags[IsNonSpeculative] = true;
85 }
86
87 %(BasicExecDeclare)s
88
89 std::string
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91 };
92 }};
93
94 output decoder {{
95 std::string
96 FailUnimplemented::generateDisassembly(Addr pc,
97 const SymbolTable *symtab) const
98 {
99 return csprintf("%-10s (unimplemented)", mnemonic);
100 }
101
102 std::string
103 WarnUnimplemented::generateDisassembly(Addr pc,
104 const SymbolTable *symtab) const
105 {
106 #ifdef SS_COMPATIBLE_DISASSEMBLY
107 return csprintf("%-10s", mnemonic);
108 #else
109 return csprintf("%-10s (unimplemented)", mnemonic);
110 #endif
111 }
112 }};
113
114 output exec {{
115 Fault
116 FailUnimplemented::execute(%(CPU_exec_context)s *xc,
117 Trace::InstRecord *traceData) const
118 {
119 panic("attempt to execute unimplemented instruction '%s' "
120 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
121 return new UnimplementedOpcodeFault;
122 }
123
124 Fault
125 WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
126 Trace::InstRecord *traceData) const
127 {
128 if (!warned) {
129 warn("instruction '%s' unimplemented\n", mnemonic);
130 warned = true;
131 }
132
133 return NoFault;
134 }
135 }};
136
137
138 def format FailUnimpl() {{
139 iop = InstObjParams(name, 'FailUnimplemented')
140 decode_block = BasicDecodeWithMnemonic.subst(iop)
141 }};
142
143 def format WarnUnimpl() {{
144 iop = InstObjParams(name, 'WarnUnimplemented')
145 decode_block = BasicDecodeWithMnemonic.subst(iop)
146 }};
147
148 output header {{
149 /**
150 * Static instruction class for unknown (illegal) instructions.
151 * These cause simulator termination if they are executed in a
152 * non-speculative mode. This is a leaf class.
153 */
154 class Unknown : public AlphaStaticInst
155 {
156 public:
157 /// Constructor
158 Unknown(ExtMachInst _machInst)
159 : AlphaStaticInst("unknown", _machInst, No_OpClass)
160 {
161 // don't call execute() (which panics) if we're on a
162 // speculative path
163 flags[IsNonSpeculative] = true;
164 }
165
166 %(BasicExecDeclare)s
167
168 std::string
169 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
170 };
171 }};
172