2 * Copyright (c) 2009 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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33 #include "arch/alpha/isa.hh"
34 #include "base/misc.hh"
35 #include "cpu/thread_context.hh"
36 #include "sim/serialize.hh"
42 ISA::serialize(EventManager
*em
, std::ostream
&os
)
44 SERIALIZE_SCALAR(fpcr
);
45 SERIALIZE_SCALAR(uniq
);
46 SERIALIZE_SCALAR(lock_flag
);
47 SERIALIZE_SCALAR(lock_addr
);
48 SERIALIZE_ARRAY(ipr
, NumInternalProcRegs
);
52 ISA::unserialize(EventManager
*em
, Checkpoint
*cp
, const std::string
§ion
)
54 UNSERIALIZE_SCALAR(fpcr
);
55 UNSERIALIZE_SCALAR(uniq
);
56 UNSERIALIZE_SCALAR(lock_flag
);
57 UNSERIALIZE_SCALAR(lock_addr
);
58 UNSERIALIZE_ARRAY(ipr
, NumInternalProcRegs
);
63 ISA::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
70 case MISCREG_LOCKFLAG
:
72 case MISCREG_LOCKADDR
:
77 assert(misc_reg
< NumInternalProcRegs
);
83 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
, ThreadID tid
)
90 case MISCREG_LOCKFLAG
:
92 case MISCREG_LOCKADDR
:
97 return readIpr(misc_reg
, tc
);
102 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
111 case MISCREG_LOCKFLAG
:
114 case MISCREG_LOCKADDR
:
121 assert(misc_reg
< NumInternalProcRegs
);
128 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
,
138 case MISCREG_LOCKFLAG
:
141 case MISCREG_LOCKADDR
:
148 setIpr(misc_reg
, val
, tc
);