src/arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  33 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  34
  35 namespace LittleEndianGuest {}
  36
  37 #include "arch/alpha/ipr.hh"
  38 #include "arch/alpha/max_inst_regs.hh"
  39 #include "arch/alpha/types.hh"
  40 #include "base/types.hh"
  41 #include "config/full_system.hh"
  42
  43 class StaticInstPtr;
  44
  45 namespace AlphaISA {
  46
  47 using namespace LittleEndianGuest;
  48 using AlphaISAInst::MaxInstSrcRegs;
  49 using AlphaISAInst::MaxInstDestRegs;
  50
  51 // These enumerate all the registers for dependence tracking.
  52 enum DependenceTags {
  53     // 0..31 are the integer regs 0..31
  54     // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  55     FP_Base_DepTag = 40,
  56     Ctrl_Base_DepTag = 72
  57 };
  58
  59 StaticInstPtr decodeInst(ExtMachInst);
  60
  61 // Alpha Does NOT have a delay slot
  62 #define ISA_HAS_DELAY_SLOT 0
  63
  64 const Addr PageShift = 13;
  65 const Addr PageBytes = ULL(1) << PageShift;
  66 const Addr PageMask = ~(PageBytes - 1);
  67 const Addr PageOffset = PageBytes - 1;
  68
  69 ////////////////////////////////////////////////////////////////////////
  70 //
  71 //  Translation stuff
  72 //
  73
  74 const Addr PteShift = 3;
  75 const Addr NPtePageShift = PageShift - PteShift;
  76 const Addr NPtePage = ULL(1) << NPtePageShift;
  77 const Addr PteMask = NPtePage - 1;
  78
  79 // User Virtual
  80 const Addr USegBase = ULL(0x0);
  81 const Addr USegEnd = ULL(0x000003ffffffffff);
  82
  83 // Kernel Direct Mapped
  84 const Addr K0SegBase = ULL(0xfffffc0000000000);
  85 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
  86
  87 // Kernel Virtual
  88 const Addr K1SegBase = ULL(0xfffffe0000000000);
  89 const Addr K1SegEnd = ULL(0xffffffffffffffff);
  90
  91 // For loading... XXX This maybe could be USegEnd?? --ali
  92 const Addr LoadAddrMask = ULL(0xffffffffff);
  93
  94 ////////////////////////////////////////////////////////////////////////
  95 //
  96 //  Interrupt levels
  97 //
  98 enum InterruptLevels
  99 {
 100     INTLEVEL_SOFTWARE_MIN = 4,
 101     INTLEVEL_SOFTWARE_MAX = 19,
 102
 103     INTLEVEL_EXTERNAL_MIN = 20,
 104     INTLEVEL_EXTERNAL_MAX = 34,
 105
 106     INTLEVEL_IRQ0 = 20,
 107     INTLEVEL_IRQ1 = 21,
 108     INTINDEX_ETHERNET = 0,
 109     INTINDEX_SCSI = 1,
 110     INTLEVEL_IRQ2 = 22,
 111     INTLEVEL_IRQ3 = 23,
 112
 113     INTLEVEL_SERIAL = 33,
 114
 115     NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 116 };
 117
 118 // EV5 modes
 119 enum mode_type
 120 {
 121     mode_kernel = 0,        // kernel
 122     mode_executive = 1,     // executive (unused by unix)
 123     mode_supervisor = 2,    // supervisor (unused by unix)
 124     mode_user = 3,          // user mode
 125     mode_number             // number of modes
 126 };
 127
 128 // Constants Related to the number of registers
 129
 130 enum {
 131     NumIntArchRegs = 32,
 132     NumPALShadowRegs = 8,
 133     NumFloatArchRegs = 32,
 134     // @todo: Figure out what this number really should be.
 135     NumMiscArchRegs = 77,
 136
 137     NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
 138     NumFloatRegs = NumFloatArchRegs,
 139     NumMiscRegs = NumMiscArchRegs,
 140
 141     TotalNumRegs =
 142         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs,
 143
 144     TotalDataRegs = NumIntRegs + NumFloatRegs,
 145
 146     // semantically meaningful register indices
 147     ZeroReg = 31,     // architecturally meaningful
 148     // the rest of these depend on the ABI
 149     StackPointerReg = 30,
 150     GlobalPointerReg = 29,
 151     ProcedureValueReg = 27,
 152     ReturnAddressReg = 26,
 153     ReturnValueReg = 0,
 154     FramePointerReg = 15,
 155
 156     SyscallNumReg = 0,
 157     FirstArgumentReg = 16,
 158     SyscallPseudoReturnReg = 20,
 159     SyscallSuccessReg = 19,
 160
 161     LogVMPageSize = 13,       // 8K bytes
 162     VMPageSize = (1 << LogVMPageSize),
 163
 164     BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
 165
 166     MachineBytes = 8,
 167     WordBytes = 4,
 168     HalfwordBytes = 2,
 169     ByteBytes = 1,
 170 };
 171
 172 // return a no-op instruction... used for instruction fetch faults
 173 // Alpha UNOP (ldq_u r31,0(r0))
 174 const ExtMachInst NoopMachInst = 0x2ffe0000;
 175
 176 } // namespace AlphaISA
 177
 178 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__