src/arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  33 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  34
  35 namespace LittleEndianGuest {}
  36
  37 #include "arch/alpha/ipr.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "base/types.hh"
  40 #include "cpu/static_inst_fwd.hh"
  41
  42 namespace AlphaISA {
  43
  44 using namespace LittleEndianGuest;
  45
  46 StaticInstPtr decodeInst(ExtMachInst);
  47
  48 // Alpha Does NOT have a delay slot
  49 #define ISA_HAS_DELAY_SLOT 0
  50
  51 const Addr PageShift = 13;
  52 const Addr PageBytes = ULL(1) << PageShift;
  53 const Addr PageMask = ~(PageBytes - 1);
  54 const Addr PageOffset = PageBytes - 1;
  55
  56 ////////////////////////////////////////////////////////////////////////
  57 //
  58 //  Translation stuff
  59 //
  60
  61 const Addr PteShift = 3;
  62 const Addr NPtePageShift = PageShift - PteShift;
  63 const Addr NPtePage = ULL(1) << NPtePageShift;
  64 const Addr PteMask = NPtePage - 1;
  65
  66 // User Virtual
  67 const Addr USegBase = ULL(0x0);
  68 const Addr USegEnd = ULL(0x000003ffffffffff);
  69
  70 // Kernel Direct Mapped
  71 const Addr K0SegBase = ULL(0xfffffc0000000000);
  72 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
  73
  74 // Kernel Virtual
  75 const Addr K1SegBase = ULL(0xfffffe0000000000);
  76 const Addr K1SegEnd = ULL(0xffffffffffffffff);
  77
  78 ////////////////////////////////////////////////////////////////////////
  79 //
  80 //  Interrupt levels
  81 //
  82 enum InterruptLevels
  83 {
  84     INTLEVEL_SOFTWARE_MIN = 4,
  85     INTLEVEL_SOFTWARE_MAX = 19,
  86
  87     INTLEVEL_EXTERNAL_MIN = 20,
  88     INTLEVEL_EXTERNAL_MAX = 34,
  89
  90     INTLEVEL_IRQ0 = 20,
  91     INTLEVEL_IRQ1 = 21,
  92     INTINDEX_ETHERNET = 0,
  93     INTINDEX_SCSI = 1,
  94     INTLEVEL_IRQ2 = 22,
  95     INTLEVEL_IRQ3 = 23,
  96
  97     INTLEVEL_SERIAL = 33,
  98
  99     NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 100 };
 101
 102 // EV5 modes
 103 enum mode_type
 104 {
 105     mode_kernel = 0,        // kernel
 106     mode_executive = 1,     // executive (unused by unix)
 107     mode_supervisor = 2,    // supervisor (unused by unix)
 108     mode_user = 3,          // user mode
 109     mode_number             // number of modes
 110 };
 111
 112 const int MachineBytes = 8;
 113
 114 // return a no-op instruction... used for instruction fetch faults
 115 // Alpha UNOP (ldq_u r31,0(r0))
 116 const ExtMachInst NoopMachInst = 0x2ffe0000;
 117
 118 // Memory accesses cannot be unaligned
 119 const bool HasUnalignedMemAcc = false;
 120
 121 const bool CurThreadInfoImplemented = true;
 122 const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23;
 123
 124 } // namespace AlphaISA
 125
 126 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__