src/arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  33 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  34
  35 namespace LittleEndianGuest {}
  36
  37 #include "arch/alpha/types.hh"
  38 #include "base/types.hh"
  39 #include "cpu/static_inst_fwd.hh"
  40
  41 namespace AlphaISA {
  42
  43 using namespace LittleEndianGuest;
  44
  45 StaticInstPtr decodeInst(ExtMachInst);
  46
  47 // Alpha Does NOT have a delay slot
  48 #define ISA_HAS_DELAY_SLOT 0
  49
  50 const Addr PageShift = 13;
  51 const Addr PageBytes = ULL(1) << PageShift;
  52 const Addr PageMask = ~(PageBytes - 1);
  53 const Addr PageOffset = PageBytes - 1;
  54
  55 ////////////////////////////////////////////////////////////////////////
  56 //
  57 //  Translation stuff
  58 //
  59
  60 const Addr PteShift = 3;
  61 const Addr NPtePageShift = PageShift - PteShift;
  62 const Addr NPtePage = ULL(1) << NPtePageShift;
  63 const Addr PteMask = NPtePage - 1;
  64
  65 // User Virtual
  66 const Addr USegBase = ULL(0x0);
  67 const Addr USegEnd = ULL(0x000003ffffffffff);
  68
  69 // Kernel Direct Mapped
  70 const Addr K0SegBase = ULL(0xfffffc0000000000);
  71 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
  72
  73 // Kernel Virtual
  74 const Addr K1SegBase = ULL(0xfffffe0000000000);
  75 const Addr K1SegEnd = ULL(0xffffffffffffffff);
  76
  77 ////////////////////////////////////////////////////////////////////////
  78 //
  79 //  Interrupt levels
  80 //
  81 enum InterruptLevels
  82 {
  83     INTLEVEL_SOFTWARE_MIN = 4,
  84     INTLEVEL_SOFTWARE_MAX = 19,
  85
  86     INTLEVEL_EXTERNAL_MIN = 20,
  87     INTLEVEL_EXTERNAL_MAX = 34,
  88
  89     INTLEVEL_IRQ0 = 20,
  90     INTLEVEL_IRQ1 = 21,
  91     INTINDEX_ETHERNET = 0,
  92     INTINDEX_SCSI = 1,
  93     INTLEVEL_IRQ2 = 22,
  94     INTLEVEL_IRQ3 = 23,
  95
  96     INTLEVEL_SERIAL = 33,
  97
  98     NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
  99 };
 100
 101 // EV5 modes
 102 enum mode_type
 103 {
 104     mode_kernel = 0,        // kernel
 105     mode_executive = 1,     // executive (unused by unix)
 106     mode_supervisor = 2,    // supervisor (unused by unix)
 107     mode_user = 3,          // user mode
 108     mode_number             // number of modes
 109 };
 110
 111 // Constants Related to the number of registers
 112
 113 enum {
 114     LogVMPageSize = 13,       // 8K bytes
 115     VMPageSize = (1 << LogVMPageSize),
 116
 117     BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
 118
 119     MachineBytes = 8,
 120     WordBytes = 4,
 121     HalfwordBytes = 2,
 122     ByteBytes = 1,
 123 };
 124
 125 // return a no-op instruction... used for instruction fetch faults
 126 // Alpha UNOP (ldq_u r31,0(r0))
 127 const ExtMachInst NoopMachInst = 0x2ffe0000;
 128
 129 // Memory accesses cannot be unaligned
 130 const bool HasUnalignedMemAcc = false;
 131
 132 } // namespace AlphaISA
 133
 134 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__