src/arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  33 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  34
  35 namespace LittleEndianGuest {}
  36
  37 #include "arch/alpha/ipr.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "config/full_system.hh"
  40 #include "sim/host.hh"
  41
  42 class StaticInstPtr;
  43
  44 namespace AlphaISA
  45 {
  46     using namespace LittleEndianGuest;
  47
  48     // These enumerate all the registers for dependence tracking.
  49     enum DependenceTags {
  50         // 0..31 are the integer regs 0..31
  51         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  52         FP_Base_DepTag = 40,
  53         Ctrl_Base_DepTag = 72
  54     };
  55
  56     StaticInstPtr decodeInst(ExtMachInst);
  57
  58     // Alpha Does NOT have a delay slot
  59     #define ISA_HAS_DELAY_SLOT 0
  60
  61     const Addr PageShift = 13;
  62     const Addr PageBytes = ULL(1) << PageShift;
  63     const Addr PageMask = ~(PageBytes - 1);
  64     const Addr PageOffset = PageBytes - 1;
  65
  66 #if FULL_SYSTEM
  67
  68     ////////////////////////////////////////////////////////////////////////
  69     //
  70     //  Translation stuff
  71     //
  72
  73    const Addr PteShift = 3;
  74     const Addr NPtePageShift = PageShift - PteShift;
  75     const Addr NPtePage = ULL(1) << NPtePageShift;
  76     const Addr PteMask = NPtePage - 1;
  77
  78     // User Virtual
  79     const Addr USegBase = ULL(0x0);
  80     const Addr USegEnd = ULL(0x000003ffffffffff);
  81
  82     // Kernel Direct Mapped
  83     const Addr K0SegBase = ULL(0xfffffc0000000000);
  84     const Addr K0SegEnd = ULL(0xfffffdffffffffff);
  85
  86     // Kernel Virtual
  87     const Addr K1SegBase = ULL(0xfffffe0000000000);
  88     const Addr K1SegEnd = ULL(0xffffffffffffffff);
  89
  90     // For loading... XXX This maybe could be USegEnd?? --ali
  91     const Addr LoadAddrMask = ULL(0xffffffffff);
  92
  93     ////////////////////////////////////////////////////////////////////////
  94     //
  95     //  Interrupt levels
  96     //
  97     enum InterruptLevels
  98     {
  99         INTLEVEL_SOFTWARE_MIN = 4,
 100         INTLEVEL_SOFTWARE_MAX = 19,
 101
 102         INTLEVEL_EXTERNAL_MIN = 20,
 103         INTLEVEL_EXTERNAL_MAX = 34,
 104
 105         INTLEVEL_IRQ0 = 20,
 106         INTLEVEL_IRQ1 = 21,
 107         INTINDEX_ETHERNET = 0,
 108         INTINDEX_SCSI = 1,
 109         INTLEVEL_IRQ2 = 22,
 110         INTLEVEL_IRQ3 = 23,
 111
 112         INTLEVEL_SERIAL = 33,
 113
 114         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 115     };
 116
 117     // EV5 modes
 118     enum mode_type
 119     {
 120         mode_kernel = 0,                // kernel
 121         mode_executive = 1,             // executive (unused by unix)
 122         mode_supervisor = 2,    // supervisor (unused by unix)
 123         mode_user = 3,          // user mode
 124         mode_number                     // number of modes
 125     };
 126
 127 #endif
 128
 129     // Constants Related to the number of registers
 130
 131     const int NumIntArchRegs = 32;
 132     const int NumPALShadowRegs = 8;
 133     const int NumFloatArchRegs = 32;
 134     // @todo: Figure out what this number really should be.
 135     const int NumMiscArchRegs = 32;
 136
 137     const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
 138     const int NumFloatRegs = NumFloatArchRegs;
 139     const int NumMiscRegs = NumMiscArchRegs;
 140
 141     const int TotalNumRegs = NumIntRegs + NumFloatRegs +
 142         NumMiscRegs + NumInternalProcRegs;
 143
 144     const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 145
 146     // Static instruction parameters
 147     const int MaxInstSrcRegs = 3;
 148     const int MaxInstDestRegs = 2;
 149
 150     // semantically meaningful register indices
 151     const int ZeroReg = 31;     // architecturally meaningful
 152     // the rest of these depend on the ABI
 153     const int StackPointerReg = 30;
 154     const int GlobalPointerReg = 29;
 155     const int ProcedureValueReg = 27;
 156     const int ReturnAddressReg = 26;
 157     const int ReturnValueReg = 0;
 158     const int FramePointerReg = 15;
 159     const int ArgumentReg0 = 16;
 160     const int ArgumentReg1 = 17;
 161     const int ArgumentReg2 = 18;
 162     const int ArgumentReg3 = 19;
 163     const int ArgumentReg4 = 20;
 164     const int ArgumentReg5 = 21;
 165     const int SyscallNumReg = ReturnValueReg;
 166     const int SyscallPseudoReturnReg = ArgumentReg4;
 167     const int SyscallSuccessReg = 19;
 168
 169     const int LogVMPageSize = 13;       // 8K bytes
 170     const int VMPageSize = (1 << LogVMPageSize);
 171
 172     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 173
 174     const int MachineBytes = 8;
 175     const int WordBytes = 4;
 176     const int HalfwordBytes = 2;
 177     const int ByteBytes = 1;
 178
 179     // return a no-op instruction... used for instruction fetch faults
 180     // Alpha UNOP (ldq_u r31,0(r0))
 181     const ExtMachInst NoopMachInst = 0x2ffe0000;
 182
 183 };
 184
 185 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__