src/arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  33 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  34
  35 namespace LittleEndianGuest {}
  36
  37 #include "arch/alpha/ipr.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "config/full_system.hh"
  40 #include "sim/host.hh"
  41
  42 class StaticInstPtr;
  43
  44 namespace AlphaISA
  45 {
  46     using namespace LittleEndianGuest;
  47
  48     // These enumerate all the registers for dependence tracking.
  49     enum DependenceTags {
  50         // 0..31 are the integer regs 0..31
  51         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  52         FP_Base_DepTag = 40,
  53         Ctrl_Base_DepTag = 72,
  54         Fpcr_DepTag = 72,               // floating point control register
  55         Uniq_DepTag = 73,
  56         Lock_Flag_DepTag = 74,
  57         Lock_Addr_DepTag = 75,
  58         Intr_Flag_DepTag = 76,
  59         IPR_Base_DepTag = 77
  60     };
  61
  62     StaticInstPtr decodeInst(ExtMachInst);
  63
  64     // Alpha Does NOT have a delay slot
  65     #define ISA_HAS_DELAY_SLOT 0
  66
  67     const Addr PageShift = 13;
  68     const Addr PageBytes = ULL(1) << PageShift;
  69     const Addr PageMask = ~(PageBytes - 1);
  70     const Addr PageOffset = PageBytes - 1;
  71
  72 #if FULL_SYSTEM
  73
  74     ////////////////////////////////////////////////////////////////////////
  75     //
  76     //  Translation stuff
  77     //
  78
  79    const Addr PteShift = 3;
  80     const Addr NPtePageShift = PageShift - PteShift;
  81     const Addr NPtePage = ULL(1) << NPtePageShift;
  82     const Addr PteMask = NPtePage - 1;
  83
  84     // User Virtual
  85     const Addr USegBase = ULL(0x0);
  86     const Addr USegEnd = ULL(0x000003ffffffffff);
  87
  88     // Kernel Direct Mapped
  89     const Addr K0SegBase = ULL(0xfffffc0000000000);
  90     const Addr K0SegEnd = ULL(0xfffffdffffffffff);
  91
  92     // Kernel Virtual
  93     const Addr K1SegBase = ULL(0xfffffe0000000000);
  94     const Addr K1SegEnd = ULL(0xffffffffffffffff);
  95
  96     // For loading... XXX This maybe could be USegEnd?? --ali
  97     const Addr LoadAddrMask = ULL(0xffffffffff);
  98
  99     ////////////////////////////////////////////////////////////////////////
 100     //
 101     //  Interrupt levels
 102     //
 103     enum InterruptLevels
 104     {
 105         INTLEVEL_SOFTWARE_MIN = 4,
 106         INTLEVEL_SOFTWARE_MAX = 19,
 107
 108         INTLEVEL_EXTERNAL_MIN = 20,
 109         INTLEVEL_EXTERNAL_MAX = 34,
 110
 111         INTLEVEL_IRQ0 = 20,
 112         INTLEVEL_IRQ1 = 21,
 113         INTINDEX_ETHERNET = 0,
 114         INTINDEX_SCSI = 1,
 115         INTLEVEL_IRQ2 = 22,
 116         INTLEVEL_IRQ3 = 23,
 117
 118         INTLEVEL_SERIAL = 33,
 119
 120         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 121     };
 122
 123
 124     // EV5 modes
 125     enum mode_type
 126     {
 127         mode_kernel = 0,                // kernel
 128         mode_executive = 1,             // executive (unused by unix)
 129         mode_supervisor = 2,    // supervisor (unused by unix)
 130         mode_user = 3,          // user mode
 131         mode_number                     // number of modes
 132     };
 133
 134 #endif
 135
 136     // Constants Related to the number of registers
 137
 138     const int NumIntArchRegs = 32;
 139     const int NumPALShadowRegs = 8;
 140     const int NumFloatArchRegs = 32;
 141     // @todo: Figure out what this number really should be.
 142     const int NumMiscArchRegs = 32;
 143
 144     const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
 145     const int NumFloatRegs = NumFloatArchRegs;
 146     const int NumMiscRegs = NumMiscArchRegs;
 147
 148     const int TotalNumRegs = NumIntRegs + NumFloatRegs +
 149         NumMiscRegs + NumInternalProcRegs;
 150
 151     const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 152
 153     // Static instruction parameters
 154     const int MaxInstSrcRegs = 3;
 155     const int MaxInstDestRegs = 2;
 156
 157     // semantically meaningful register indices
 158     const int ZeroReg = 31;     // architecturally meaningful
 159     // the rest of these depend on the ABI
 160     const int StackPointerReg = 30;
 161     const int GlobalPointerReg = 29;
 162     const int ProcedureValueReg = 27;
 163     const int ReturnAddressReg = 26;
 164     const int ReturnValueReg = 0;
 165     const int FramePointerReg = 15;
 166     const int ArgumentReg0 = 16;
 167     const int ArgumentReg1 = 17;
 168     const int ArgumentReg2 = 18;
 169     const int ArgumentReg3 = 19;
 170     const int ArgumentReg4 = 20;
 171     const int ArgumentReg5 = 21;
 172     const int SyscallNumReg = ReturnValueReg;
 173     const int SyscallPseudoReturnReg = ArgumentReg4;
 174     const int SyscallSuccessReg = 19;
 175
 176     const int LogVMPageSize = 13;       // 8K bytes
 177     const int VMPageSize = (1 << LogVMPageSize);
 178
 179     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 180
 181     const int MachineBytes = 8;
 182     const int WordBytes = 4;
 183     const int HalfwordBytes = 2;
 184     const int ByteBytes = 1;
 185
 186     // return a no-op instruction... used for instruction fetch faults
 187     // Alpha UNOP (ldq_u r31,0(r0))
 188     const ExtMachInst NoopMachInst = 0x2ffe0000;
 189
 190     // redirected register map, really only used for the full system case.
 191     extern const int reg_redir[NumIntRegs];
 192
 193 };
 194
 195 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__