src/arch/alpha/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  *          Kevin Lim
  31  */
  32
  33 #include <cassert>
  34
  35 #include "arch/alpha/miscregfile.hh"
  36 #include "base/misc.hh"
  37
  38 namespace AlphaISA {
  39
  40 void
  41 MiscRegFile::serialize(std::ostream &os)
  42 {
  43     SERIALIZE_SCALAR(fpcr);
  44     SERIALIZE_SCALAR(uniq);
  45     SERIALIZE_SCALAR(lock_flag);
  46     SERIALIZE_SCALAR(lock_addr);
  47     SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  48 }
  49
  50 void
  51 MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
  52 {
  53     UNSERIALIZE_SCALAR(fpcr);
  54     UNSERIALIZE_SCALAR(uniq);
  55     UNSERIALIZE_SCALAR(lock_flag);
  56     UNSERIALIZE_SCALAR(lock_addr);
  57     UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  58 }
  59
  60 MiscReg
  61 MiscRegFile::readRegNoEffect(int misc_reg)
  62 {
  63     switch (misc_reg) {
  64       case MISCREG_FPCR:
  65         return fpcr;
  66       case MISCREG_UNIQ:
  67         return uniq;
  68       case MISCREG_LOCKFLAG:
  69         return lock_flag;
  70       case MISCREG_LOCKADDR:
  71         return lock_addr;
  72       case MISCREG_INTR:
  73         return intr_flag;
  74       default:
  75         assert(misc_reg < NumInternalProcRegs);
  76         return ipr[misc_reg];
  77     }
  78 }
  79
  80 MiscReg
  81 MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
  82 {
  83     switch (misc_reg) {
  84       case MISCREG_FPCR:
  85         return fpcr;
  86       case MISCREG_UNIQ:
  87         return uniq;
  88       case MISCREG_LOCKFLAG:
  89         return lock_flag;
  90       case MISCREG_LOCKADDR:
  91         return lock_addr;
  92       case MISCREG_INTR:
  93         return intr_flag;
  94       default:
  95         return readIpr(misc_reg, tc);
  96     }
  97 }
  98
  99 void
 100 MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
 101 {
 102     switch (misc_reg) {
 103       case MISCREG_FPCR:
 104         fpcr = val;
 105         return;
 106       case MISCREG_UNIQ:
 107         uniq = val;
 108         return;
 109       case MISCREG_LOCKFLAG:
 110         lock_flag = val;
 111         return;
 112       case MISCREG_LOCKADDR:
 113         lock_addr = val;
 114         return;
 115       case MISCREG_INTR:
 116         intr_flag = val;
 117         return;
 118       default:
 119         assert(misc_reg < NumInternalProcRegs);
 120         ipr[misc_reg] = val;
 121         return;
 122     }
 123 }
 124
 125 void
 126 MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
 127 {
 128     switch (misc_reg) {
 129       case MISCREG_FPCR:
 130         fpcr = val;
 131         return;
 132       case MISCREG_UNIQ:
 133         uniq = val;
 134         return;
 135       case MISCREG_LOCKFLAG:
 136         lock_flag = val;
 137         return;
 138       case MISCREG_LOCKADDR:
 139         lock_addr = val;
 140         return;
 141       case MISCREG_INTR:
 142         intr_flag = val;
 143         return;
 144       default:
 145         setIpr(misc_reg, val, tc);
 146         return;
 147     }
 148 }
 149
 150 } // namespace AlphaISA