src/arch/alpha/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  *          Kevin Lim
  31  */
  32
  33 #include <cassert>
  34
  35 #include "arch/alpha/miscregfile.hh"
  36 #include "base/misc.hh"
  37
  38 namespace AlphaISA {
  39
  40 void
  41 MiscRegFile::serialize(std::ostream &os)
  42 {
  43     SERIALIZE_SCALAR(fpcr);
  44     SERIALIZE_SCALAR(uniq);
  45     SERIALIZE_SCALAR(lock_flag);
  46     SERIALIZE_SCALAR(lock_addr);
  47     SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  48 }
  49
  50 void
  51 MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
  52 {
  53     UNSERIALIZE_SCALAR(fpcr);
  54     UNSERIALIZE_SCALAR(uniq);
  55     UNSERIALIZE_SCALAR(lock_flag);
  56     UNSERIALIZE_SCALAR(lock_addr);
  57     UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  58 }
  59
  60 MiscRegFile::MiscRegFile(BaseCPU *_cpu)
  61 {
  62     cpu = _cpu;
  63     initializeIprTable();
  64 }
  65
  66
  67 MiscReg
  68 MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid)
  69 {
  70     switch (misc_reg) {
  71       case MISCREG_FPCR:
  72         return fpcr;
  73       case MISCREG_UNIQ:
  74         return uniq;
  75       case MISCREG_LOCKFLAG:
  76         return lock_flag;
  77       case MISCREG_LOCKADDR:
  78         return lock_addr;
  79       case MISCREG_INTR:
  80         return intr_flag;
  81       default:
  82         assert(misc_reg < NumInternalProcRegs);
  83         return ipr[misc_reg];
  84     }
  85 }
  86
  87 MiscReg
  88 MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid)
  89 {
  90     switch (misc_reg) {
  91       case MISCREG_FPCR:
  92         return fpcr;
  93       case MISCREG_UNIQ:
  94         return uniq;
  95       case MISCREG_LOCKFLAG:
  96         return lock_flag;
  97       case MISCREG_LOCKADDR:
  98         return lock_addr;
  99       case MISCREG_INTR:
 100         return intr_flag;
 101       default:
 102         return readIpr(misc_reg, tc);
 103     }
 104 }
 105
 106 void
 107 MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 108 {
 109     switch (misc_reg) {
 110       case MISCREG_FPCR:
 111         fpcr = val;
 112         return;
 113       case MISCREG_UNIQ:
 114         uniq = val;
 115         return;
 116       case MISCREG_LOCKFLAG:
 117         lock_flag = val;
 118         return;
 119       case MISCREG_LOCKADDR:
 120         lock_addr = val;
 121         return;
 122       case MISCREG_INTR:
 123         intr_flag = val;
 124         return;
 125       default:
 126         assert(misc_reg < NumInternalProcRegs);
 127         ipr[misc_reg] = val;
 128         return;
 129     }
 130 }
 131
 132 void
 133 MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
 134                     ThreadID tid)
 135 {
 136     switch (misc_reg) {
 137       case MISCREG_FPCR:
 138         fpcr = val;
 139         return;
 140       case MISCREG_UNIQ:
 141         uniq = val;
 142         return;
 143       case MISCREG_LOCKFLAG:
 144         lock_flag = val;
 145         return;
 146       case MISCREG_LOCKADDR:
 147         lock_addr = val;
 148         return;
 149       case MISCREG_INTR:
 150         intr_flag = val;
 151         return;
 152       default:
 153         setIpr(misc_reg, val, tc);
 154         return;
 155     }
 156 }
 157
 158 } // namespace AlphaISA