src/arch/alpha/miscregfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Gabe Black
  30  */
  31
  32 #ifndef __ARCH_ALPHA_MISCREGFILE_HH__
  33 #define __ARCH_ALPHA_MISCREGFILE_HH__
  34
  35 #include <iosfwd>
  36
  37 #include "arch/alpha/ipr.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "base/types.hh"
  40 #include "sim/serialize.hh"
  41
  42 class Checkpoint;
  43 class ThreadContext;
  44 class BaseCPU;
  45
  46 namespace AlphaISA {
  47
  48 enum MiscRegIndex
  49 {
  50     MISCREG_FPCR = NumInternalProcRegs,
  51     MISCREG_UNIQ,
  52     MISCREG_LOCKFLAG,
  53     MISCREG_LOCKADDR,
  54     MISCREG_INTR
  55 };
  56
  57 class MiscRegFile
  58 {
  59   public:
  60     friend class RegFile;
  61     typedef uint64_t InternalProcReg;
  62
  63   protected:
  64     uint64_t fpcr;       // floating point condition codes
  65     uint64_t uniq;       // process-unique register
  66     bool lock_flag;      // lock flag for LL/SC
  67     Addr lock_addr;      // lock address for LL/SC
  68     int intr_flag;
  69
  70     InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
  71
  72     BaseCPU *cpu;
  73
  74   protected:
  75     InternalProcReg readIpr(int idx, ThreadContext *tc);
  76     void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
  77
  78   public:
  79     MiscRegFile()
  80     {
  81         initializeIprTable();
  82     }
  83
  84     MiscRegFile(BaseCPU *cpu);
  85
  86     // These functions should be removed once the simplescalar cpu
  87     // model has been replaced.
  88     int getInstAsid();
  89     int getDataAsid();
  90
  91     MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0);
  92     MiscReg readReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
  93
  94     void setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0);
  95     void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
  96                 ThreadID tid = 0);
  97
  98     void
  99     clear()
 100     {
 101         fpcr = 0;
 102         uniq = 0;
 103         lock_flag = 0;
 104         lock_addr = 0;
 105         intr_flag = 0;
 106     }
 107
 108     void serialize(std::ostream &os);
 109     void unserialize(Checkpoint *cp, const std::string &section);
 110
 111     void reset(std::string core_name, ThreadID num_threads,
 112                unsigned num_vpes, BaseCPU *_cpu)
 113     { }
 114
 115
 116     void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
 117     { }
 118
 119
 120 };
 121
 122 void copyIprs(ThreadContext *src, ThreadContext *dest);
 123
 124 } // namespace AlphaISA
 125
 126 #endif // __ARCH_ALPHA_MISCREGFILE_HH__