src/arch/alpha/process.cc

   1 /*
   2  * Copyright (c) 2003-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/alpha/isa_traits.hh"
  33 #include "arch/alpha/process.hh"
  34 #include "base/loader/object_file.hh"
  35 #include "base/loader/elf_object.hh"
  36 #include "base/misc.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "mem/page_table.hh"
  39 #include "sim/byteswap.hh"
  40 #include "sim/process_impl.hh"
  41 #include "sim/system.hh"
  42
  43 using namespace AlphaISA;
  44 using namespace std;
  45
  46 AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params,
  47                                    ObjectFile *objFile)
  48     : LiveProcess(params, objFile)
  49 {
  50     brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
  51     brk_point = roundUp(brk_point, VMPageSize);
  52
  53     // Set up stack.  On Alpha, stack goes below text section.  This
  54     // code should get moved to some architecture-specific spot.
  55     stack_base = objFile->textBase() - (409600+4096);
  56
  57     // Set up region for mmaps.  Tru64 seems to start just above 0 and
  58     // grow up from there.
  59     mmap_start = mmap_end = 0x10000;
  60
  61     // Set pointer for next thread stack.  Reserve 8M for main stack.
  62     next_thread_stack_base = stack_base - (8 * 1024 * 1024);
  63
  64 }
  65
  66 void
  67 AlphaLiveProcess::argsInit(int intSize, int pageSize)
  68 {
  69     objFile->loadSections(initVirtMem);
  70
  71     typedef AuxVector<uint64_t> auxv_t;
  72     std::vector<auxv_t>  auxv;
  73
  74     ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
  75     if(elfObject)
  76     {
  77         // modern glibc uses a bunch of auxiliary vectors to set up
  78         // TLS as well as do a bunch of other stuff
  79         // these vectors go on the bottom of the stack, below argc/argv/envp
  80         // pointers but above actual arg strings
  81         // I don't have all the ones glibc looks at here, but so far it doesn't
  82         // seem to be a problem.
  83         // check out _dl_aux_init() in glibc/elf/dl-support.c for details
  84         // --Lisa
  85         auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
  86         auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
  87         auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
  88         DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
  89         auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
  90         auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
  91         auxv.push_back(auxv_t(M5_AT_UID, uid()));
  92         auxv.push_back(auxv_t(M5_AT_EUID, euid()));
  93         auxv.push_back(auxv_t(M5_AT_GID, gid()));
  94         auxv.push_back(auxv_t(M5_AT_EGID, egid()));
  95
  96     }
  97
  98     // Calculate how much space we need for arg & env & auxv arrays.
  99     int argv_array_size = intSize * (argv.size() + 1);
 100     int envp_array_size = intSize * (envp.size() + 1);
 101     int auxv_array_size = intSize * 2 * (auxv.size() + 1);
 102
 103     int arg_data_size = 0;
 104     for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
 105         arg_data_size += argv[i].size() + 1;
 106     }
 107     int env_data_size = 0;
 108     for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
 109         env_data_size += envp[i].size() + 1;
 110     }
 111
 112     int space_needed =
 113         argv_array_size +
 114         envp_array_size +
 115         auxv_array_size +
 116         arg_data_size +
 117         env_data_size;
 118
 119     if (space_needed < 32*1024)
 120         space_needed = 32*1024;
 121
 122     // set bottom of stack
 123     stack_min = stack_base - space_needed;
 124     // align it
 125     stack_min = roundDown(stack_min, pageSize);
 126     stack_size = stack_base - stack_min;
 127     // map memory
 128     pTable->allocate(stack_min, roundUp(stack_size, pageSize));
 129
 130     // map out initial stack contents
 131     Addr argv_array_base = stack_min + intSize; // room for argc
 132     Addr envp_array_base = argv_array_base + argv_array_size;
 133     Addr auxv_array_base = envp_array_base + envp_array_size;
 134     Addr arg_data_base = auxv_array_base + auxv_array_size;
 135     Addr env_data_base = arg_data_base + arg_data_size;
 136
 137     // write contents to stack
 138     uint64_t argc = argv.size();
 139     if (intSize == 8)
 140         argc = htog((uint64_t)argc);
 141     else if (intSize == 4)
 142         argc = htog((uint32_t)argc);
 143     else
 144         panic("Unknown int size");
 145
 146     initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
 147
 148     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 149     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
 150
 151     //Copy the aux stuff
 152     for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
 153         initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
 154                 (uint8_t*)&(auxv[x].a_type), intSize);
 155         initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
 156                 (uint8_t*)&(auxv[x].a_val), intSize);
 157     }
 158
 159     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 160
 161     setSyscallArg(tc, 0, argc);
 162     setSyscallArg(tc, 1, argv_array_base);
 163     tc->setIntReg(StackPointerReg, stack_min);
 164
 165     Addr prog_entry = objFile->entryPoint();
 166     tc->setPC(prog_entry);
 167     tc->setNextPC(prog_entry + sizeof(MachInst));
 168
 169     // MIPS/Sparc need NNPC for delay slot handling, while
 170     // Alpha has no delay slots... However, CPU models
 171     // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this
 172     // here ensures CPU-Model Compatibility across board
 173     tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
 174 }
 175
 176 void
 177 AlphaLiveProcess::setupASNReg()
 178 {
 179     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 180     tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
 181 }
 182
 183
 184 void
 185 AlphaLiveProcess::loadState(Checkpoint *cp)
 186 {
 187     LiveProcess::loadState(cp);
 188     // need to set up ASN after unserialization since M5_pid value may
 189     // come from checkpoint
 190     setupASNReg();
 191 }
 192
 193
 194 void
 195 AlphaLiveProcess::initState()
 196 {
 197     // need to set up ASN before further initialization since init
 198     // will involve writing to virtual memory addresses
 199     setupASNReg();
 200
 201     LiveProcess::initState();
 202
 203     argsInit(MachineBytes, VMPageSize);
 204
 205     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 206     tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
 207     //Operate in user mode
 208     tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
 209     tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
 210     //No super page mapping
 211     tc->setMiscRegNoEffect(IPR_MCSR, 0);
 212 }
 213
 214 AlphaISA::IntReg
 215 AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
 216 {
 217     assert(i < 6);
 218     return tc->readIntReg(FirstArgumentReg + i++);
 219 }
 220
 221 void
 222 AlphaLiveProcess::setSyscallArg(ThreadContext *tc,
 223         int i, AlphaISA::IntReg val)
 224 {
 225     assert(i < 6);
 226     tc->setIntReg(FirstArgumentReg + i, val);
 227 }
 228
 229 void
 230 AlphaLiveProcess::setSyscallReturn(ThreadContext *tc,
 231         SyscallReturn return_value)
 232 {
 233     // check for error condition.  Alpha syscall convention is to
 234     // indicate success/failure in reg a3 (r19) and put the
 235     // return value itself in the standard return value reg (v0).
 236     if (return_value.successful()) {
 237         // no error
 238         tc->setIntReg(SyscallSuccessReg, 0);
 239         tc->setIntReg(ReturnValueReg, return_value.value());
 240     } else {
 241         // got an error, return details
 242         tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
 243         tc->setIntReg(ReturnValueReg, -return_value.value());
 244     }
 245 }