src/arch/alpha/regfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_ALPHA_REGFILE_HH__
  32 #define __ARCH_ALPHA_REGFILE_HH__
  33
  34 #include "arch/alpha/isa_traits.hh"
  35 #include "arch/alpha/floatregfile.hh"
  36 #include "arch/alpha/intregfile.hh"
  37 #include "arch/alpha/miscregfile.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "arch/alpha/mt.hh"
  40 #include "sim/faults.hh"
  41
  42 #include <string>
  43
  44 //XXX These should be implemented by someone who knows the alpha stuff better
  45
  46 class Checkpoint;
  47 class EventManager;
  48 class ThreadContext;
  49
  50 namespace AlphaISA {
  51
  52 class RegFile {
  53   protected:
  54     Addr pc;   // program counter
  55     Addr npc;  // next-cycle program counter
  56     Addr nnpc; // next next-cycle program counter
  57
  58   public:
  59     Addr
  60     readPC()
  61     {
  62         return pc;
  63     }
  64
  65     void
  66     setPC(Addr val)
  67     {
  68         pc = val;
  69     }
  70
  71     Addr
  72     readNextPC()
  73     {
  74         return npc;
  75     }
  76
  77     void
  78     setNextPC(Addr val)
  79     {
  80         npc = val;
  81     }
  82
  83     Addr
  84     readNextNPC()
  85     {
  86         return npc + sizeof(MachInst);
  87     }
  88
  89     void
  90     setNextNPC(Addr val)
  91     { }
  92
  93   protected:
  94     IntRegFile intRegFile;          // (signed) integer register file
  95     FloatRegFile floatRegFile;      // floating point register file
  96     MiscRegFile miscRegFile;        // control register file
  97
  98   public:
  99 #if FULL_SYSTEM
 100     int intrflag;                   // interrupt flag
 101
 102     int
 103     instAsid()
 104     {
 105         return miscRegFile.getInstAsid();
 106     }
 107
 108     int
 109     dataAsid()
 110     {
 111         return miscRegFile.getDataAsid();
 112     }
 113 #endif // FULL_SYSTEM
 114
 115     void
 116     clear()
 117     {
 118         intRegFile.clear();
 119         floatRegFile.clear();
 120         miscRegFile.clear();
 121     }
 122
 123     MiscReg
 124     readMiscRegNoEffect(int miscReg)
 125     {
 126         return miscRegFile.readRegNoEffect(miscReg);
 127     }
 128
 129     MiscReg
 130     readMiscReg(int miscReg, ThreadContext *tc)
 131     {
 132         return miscRegFile.readReg(miscReg, tc);
 133     }
 134
 135     void
 136     setMiscRegNoEffect(int miscReg, const MiscReg &val)
 137     {
 138         miscRegFile.setRegNoEffect(miscReg, val);
 139     }
 140
 141     void
 142     setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
 143     {
 144         miscRegFile.setReg(miscReg, val, tc);
 145     }
 146
 147     FloatReg
 148     readFloatReg(int floatReg)
 149     {
 150         return floatRegFile.d[floatReg];
 151     }
 152
 153     FloatReg
 154     readFloatReg(int floatReg, int width)
 155     {
 156         return readFloatReg(floatReg);
 157     }
 158
 159     FloatRegBits
 160     readFloatRegBits(int floatReg)
 161     {
 162         return floatRegFile.q[floatReg];
 163     }
 164
 165     FloatRegBits
 166     readFloatRegBits(int floatReg, int width)
 167     {
 168         return readFloatRegBits(floatReg);
 169     }
 170
 171     void
 172     setFloatReg(int floatReg, const FloatReg &val)
 173     {
 174         floatRegFile.d[floatReg] = val;
 175     }
 176
 177     void
 178     setFloatReg(int floatReg, const FloatReg &val, int width)
 179     {
 180         setFloatReg(floatReg, val);
 181     }
 182
 183     void
 184     setFloatRegBits(int floatReg, const FloatRegBits &val)
 185     {
 186         floatRegFile.q[floatReg] = val;
 187     }
 188
 189     void
 190     setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 191     {
 192         setFloatRegBits(floatReg, val);
 193     }
 194
 195     IntReg
 196     readIntReg(int intReg)
 197     {
 198         return intRegFile.readReg(intReg);
 199     }
 200
 201     void
 202     setIntReg(int intReg, const IntReg &val)
 203     {
 204         intRegFile.setReg(intReg, val);
 205     }
 206
 207     void serialize(EventManager *em, std::ostream &os);
 208     void unserialize(EventManager *em, Checkpoint *cp,
 209         const std::string &section);
 210 };
 211
 212 static inline int
 213 flattenIntIndex(ThreadContext * tc, int reg)
 214 {
 215     return reg;
 216 }
 217
 218 static inline int
 219 flattenFloatIndex(ThreadContext * tc, int reg)
 220 {
 221     return reg;
 222 }
 223
 224 void copyRegs(ThreadContext *src, ThreadContext *dest);
 225
 226 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 227
 228 } // namespace AlphaISA
 229
 230 #endif // __ARCH_ALPHA_REGFILE_HH__