src/arch/alpha/regfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_ALPHA_REGFILE_HH__
  32 #define __ARCH_ALPHA_REGFILE_HH__
  33
  34 #include "arch/alpha/isa_traits.hh"
  35 #include "arch/alpha/floatregfile.hh"
  36 #include "arch/alpha/intregfile.hh"
  37 #include "arch/alpha/miscregfile.hh"
  38 #include "arch/alpha/types.hh"
  39 #include "sim/faults.hh"
  40
  41 #include <string>
  42
  43 //XXX These should be implemented by someone who knows the alpha stuff better
  44
  45 class Checkpoint;
  46 class EventManager;
  47 class ThreadContext;
  48
  49 namespace AlphaISA {
  50
  51 class RegFile {
  52   protected:
  53     Addr pc;   // program counter
  54     Addr npc;  // next-cycle program counter
  55     Addr nnpc; // next next-cycle program counter
  56
  57   public:
  58     Addr
  59     readPC()
  60     {
  61         return pc;
  62     }
  63
  64     void
  65     setPC(Addr val)
  66     {
  67         pc = val;
  68     }
  69
  70     Addr
  71     readNextPC()
  72     {
  73         return npc;
  74     }
  75
  76     void
  77     setNextPC(Addr val)
  78     {
  79         npc = val;
  80     }
  81
  82     Addr
  83     readNextNPC()
  84     {
  85         return npc + sizeof(MachInst);
  86     }
  87
  88     void
  89     setNextNPC(Addr val)
  90     { }
  91
  92   protected:
  93     IntRegFile intRegFile;          // (signed) integer register file
  94     FloatRegFile floatRegFile;      // floating point register file
  95     MiscRegFile miscRegFile;        // control register file
  96
  97   public:
  98 #if FULL_SYSTEM
  99     int intrflag;                   // interrupt flag
 100
 101     int
 102     instAsid()
 103     {
 104         return miscRegFile.getInstAsid();
 105     }
 106
 107     int
 108     dataAsid()
 109     {
 110         return miscRegFile.getDataAsid();
 111     }
 112 #endif // FULL_SYSTEM
 113
 114     void
 115     clear()
 116     {
 117         intRegFile.clear();
 118         floatRegFile.clear();
 119         miscRegFile.clear();
 120     }
 121
 122     MiscReg
 123     readMiscRegNoEffect(int miscReg)
 124     {
 125         return miscRegFile.readRegNoEffect(miscReg);
 126     }
 127
 128     MiscReg
 129     readMiscReg(int miscReg, ThreadContext *tc)
 130     {
 131         return miscRegFile.readReg(miscReg, tc);
 132     }
 133
 134     void
 135     setMiscRegNoEffect(int miscReg, const MiscReg &val)
 136     {
 137         miscRegFile.setRegNoEffect(miscReg, val);
 138     }
 139
 140     void
 141     setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
 142     {
 143         miscRegFile.setReg(miscReg, val, tc);
 144     }
 145
 146     FloatReg
 147     readFloatReg(int floatReg)
 148     {
 149         return floatRegFile.d[floatReg];
 150     }
 151
 152     FloatReg
 153     readFloatReg(int floatReg, int width)
 154     {
 155         return readFloatReg(floatReg);
 156     }
 157
 158     FloatRegBits
 159     readFloatRegBits(int floatReg)
 160     {
 161         return floatRegFile.q[floatReg];
 162     }
 163
 164     FloatRegBits
 165     readFloatRegBits(int floatReg, int width)
 166     {
 167         return readFloatRegBits(floatReg);
 168     }
 169
 170     void
 171     setFloatReg(int floatReg, const FloatReg &val)
 172     {
 173         floatRegFile.d[floatReg] = val;
 174     }
 175
 176     void
 177     setFloatReg(int floatReg, const FloatReg &val, int width)
 178     {
 179         setFloatReg(floatReg, val);
 180     }
 181
 182     void
 183     setFloatRegBits(int floatReg, const FloatRegBits &val)
 184     {
 185         floatRegFile.q[floatReg] = val;
 186     }
 187
 188     void
 189     setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 190     {
 191         setFloatRegBits(floatReg, val);
 192     }
 193
 194     IntReg
 195     readIntReg(int intReg)
 196     {
 197         return intRegFile.readReg(intReg);
 198     }
 199
 200     void
 201     setIntReg(int intReg, const IntReg &val)
 202     {
 203         intRegFile.setReg(intReg, val);
 204     }
 205
 206     void serialize(EventManager *em, std::ostream &os);
 207     void unserialize(EventManager *em, Checkpoint *cp,
 208         const std::string &section);
 209
 210     void
 211     changeContext(RegContextParam param, RegContextVal val)
 212     {
 213         //This would be an alternative place to call/implement
 214         //the swapPALShadow function
 215     }
 216 };
 217
 218 static inline int
 219 flattenIntIndex(ThreadContext * tc, int reg)
 220 {
 221     return reg;
 222 }
 223
 224 static inline int
 225 flattenFloatIndex(ThreadContext * tc, int reg)
 226 {
 227     return reg;
 228 }
 229
 230 void copyRegs(ThreadContext *src, ThreadContext *dest);
 231
 232 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 233
 234 } // namespace AlphaISA
 235
 236 #endif // __ARCH_ALPHA_REGFILE_HH__