src/arch/alpha/regfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_ALPHA_REGFILE_HH__
  32 #define __ARCH_ALPHA_REGFILE_HH__
  33
  34 #include "arch/alpha/types.hh"
  35 #include "arch/alpha/isa_traits.hh"
  36 #include "sim/faults.hh"
  37
  38 #include <string>
  39
  40 //XXX These should be implemented by someone who knows the alpha stuff better
  41
  42 class Checkpoint;
  43 class ThreadContext;
  44
  45 namespace AlphaISA
  46 {
  47
  48     static inline std::string getIntRegName(RegIndex)
  49     {
  50         return "";
  51     }
  52
  53     static inline std::string getFloatRegName(RegIndex)
  54     {
  55         return "";
  56     }
  57
  58     static inline std::string getMiscRegName(RegIndex)
  59     {
  60         return "";
  61     }
  62
  63     class IntRegFile
  64     {
  65       protected:
  66         IntReg regs[NumIntRegs];
  67
  68       public:
  69
  70         IntReg readReg(int intReg)
  71         {
  72             return regs[intReg];
  73         }
  74
  75         Fault setReg(int intReg, const IntReg &val)
  76         {
  77             regs[intReg] = val;
  78             return NoFault;
  79         }
  80
  81         void serialize(std::ostream &os);
  82
  83         void unserialize(Checkpoint *cp, const std::string &section);
  84
  85         void clear()
  86         { bzero(regs, sizeof(regs)); }
  87     };
  88
  89     class FloatRegFile
  90     {
  91       public:
  92
  93         union {
  94             uint64_t q[NumFloatRegs];   // integer qword view
  95             double d[NumFloatRegs];     // double-precision floating point view
  96         };
  97
  98         void serialize(std::ostream &os);
  99
 100         void unserialize(Checkpoint *cp, const std::string &section);
 101
 102         void clear()
 103         { bzero(d, sizeof(d)); }
 104     };
 105
 106     class MiscRegFile {
 107       protected:
 108         uint64_t        fpcr;           // floating point condition codes
 109         uint64_t        uniq;           // process-unique register
 110         bool            lock_flag;      // lock flag for LL/SC
 111         Addr            lock_addr;      // lock address for LL/SC
 112         int             intr_flag;
 113
 114       public:
 115         MiscReg readReg(int misc_reg);
 116
 117         MiscReg readRegWithEffect(int misc_reg, Fault &fault,
 118                 ThreadContext *tc);
 119
 120         //These functions should be removed once the simplescalar cpu model
 121         //has been replaced.
 122         int getInstAsid();
 123         int getDataAsid();
 124
 125         Fault setReg(int misc_reg, const MiscReg &val);
 126
 127         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
 128                 ThreadContext *tc);
 129
 130         void clear()
 131         {
 132             fpcr = uniq = 0;
 133             lock_flag = 0;
 134             lock_addr = 0;
 135             intr_flag = 0;
 136         }
 137
 138         void serialize(std::ostream &os);
 139
 140         void unserialize(Checkpoint *cp, const std::string &section);
 141 #if FULL_SYSTEM
 142       protected:
 143         typedef uint64_t InternalProcReg;
 144
 145         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 146
 147       private:
 148         InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
 149
 150         Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
 151 #endif
 152         friend class RegFile;
 153     };
 154
 155     class RegFile {
 156
 157       protected:
 158         Addr pc;                        // program counter
 159         Addr npc;                       // next-cycle program counter
 160         Addr nnpc;
 161
 162       public:
 163         Addr readPC()
 164         {
 165             return pc;
 166         }
 167
 168         void setPC(Addr val)
 169         {
 170             pc = val;
 171         }
 172
 173         Addr readNextPC()
 174         {
 175             return npc;
 176         }
 177
 178         void setNextPC(Addr val)
 179         {
 180             npc = val;
 181         }
 182
 183         Addr readNextNPC()
 184         {
 185             return nnpc;
 186         }
 187
 188         void setNextNPC(Addr val)
 189         {
 190             nnpc = val;
 191         }
 192
 193       protected:
 194         IntRegFile intRegFile;          // (signed) integer register file
 195         FloatRegFile floatRegFile;      // floating point register file
 196         MiscRegFile miscRegFile;        // control register file
 197
 198       public:
 199
 200 #if FULL_SYSTEM
 201         int intrflag;                   // interrupt flag
 202         inline int instAsid()
 203         { return miscRegFile.getInstAsid(); }
 204         inline int dataAsid()
 205         { return miscRegFile.getDataAsid(); }
 206 #endif // FULL_SYSTEM
 207
 208         void clear()
 209         {
 210             intRegFile.clear();
 211             floatRegFile.clear();
 212             miscRegFile.clear();
 213         }
 214
 215         MiscReg readMiscReg(int miscReg)
 216         {
 217             return miscRegFile.readReg(miscReg);
 218         }
 219
 220         MiscReg readMiscRegWithEffect(int miscReg,
 221                 Fault &fault, ThreadContext *tc)
 222         {
 223             fault = NoFault;
 224             return miscRegFile.readRegWithEffect(miscReg, fault, tc);
 225         }
 226
 227         Fault setMiscReg(int miscReg, const MiscReg &val)
 228         {
 229             return miscRegFile.setReg(miscReg, val);
 230         }
 231
 232         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
 233                 ThreadContext * tc)
 234         {
 235             return miscRegFile.setRegWithEffect(miscReg, val, tc);
 236         }
 237
 238         FloatReg readFloatReg(int floatReg)
 239         {
 240             return floatRegFile.d[floatReg];
 241         }
 242
 243         FloatReg readFloatReg(int floatReg, int width)
 244         {
 245             return readFloatReg(floatReg);
 246         }
 247
 248         FloatRegBits readFloatRegBits(int floatReg)
 249         {
 250             return floatRegFile.q[floatReg];
 251         }
 252
 253         FloatRegBits readFloatRegBits(int floatReg, int width)
 254         {
 255             return readFloatRegBits(floatReg);
 256         }
 257
 258         Fault setFloatReg(int floatReg, const FloatReg &val)
 259         {
 260             floatRegFile.d[floatReg] = val;
 261             return NoFault;
 262         }
 263
 264         Fault setFloatReg(int floatReg, const FloatReg &val, int width)
 265         {
 266             return setFloatReg(floatReg, val);
 267         }
 268
 269         Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
 270         {
 271             floatRegFile.q[floatReg] = val;
 272             return NoFault;
 273         }
 274
 275         Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 276         {
 277             return setFloatRegBits(floatReg, val);
 278         }
 279
 280         IntReg readIntReg(int intReg)
 281         {
 282             return intRegFile.readReg(intReg);
 283         }
 284
 285         Fault setIntReg(int intReg, const IntReg &val)
 286         {
 287             return intRegFile.setReg(intReg, val);
 288         }
 289
 290         void serialize(std::ostream &os);
 291         void unserialize(Checkpoint *cp, const std::string &section);
 292
 293         void changeContext(RegContextParam param, RegContextVal val)
 294         {
 295             //This would be an alternative place to call/implement
 296             //the swapPALShadow function
 297         }
 298     };
 299
 300     void copyRegs(ThreadContext *src, ThreadContext *dest);
 301
 302     void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 303
 304 #if FULL_SYSTEM
 305     void copyIprs(ThreadContext *src, ThreadContext *dest);
 306 #endif
 307 } // namespace AlphaISA
 308
 309 #endif