2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
36 #include "arch/alpha/pagetable.hh"
37 #include "arch/alpha/tlb.hh"
38 #include "arch/alpha/faults.hh"
39 #include "base/inifile.hh"
40 #include "base/str.hh"
41 #include "base/trace.hh"
42 #include "config/alpha_tlaser.hh"
43 #include "cpu/thread_context.hh"
49 ///////////////////////////////////////////////////////////////////////
54 bool uncacheBit39
= false;
55 bool uncacheBit40
= false;
58 #define MODE2MASK(X) (1 << (X))
60 TLB::TLB(const Params
*p
)
61 : BaseTLB(p
), size(p
->size
), nlu(0)
63 table
= new TlbEntry
[size
];
64 memset(table
, 0, sizeof(TlbEntry
[size
]));
74 // look up an entry in the TLB
76 TLB::lookup(Addr vpn
, uint8_t asn
)
78 // assume not found...
79 TlbEntry
*retval
= NULL
;
82 if (vpn
== EntryCache
[0]->tag
&&
83 (EntryCache
[0]->asma
|| EntryCache
[0]->asn
== asn
))
84 retval
= EntryCache
[0];
85 else if (EntryCache
[1]) {
86 if (vpn
== EntryCache
[1]->tag
&&
87 (EntryCache
[1]->asma
|| EntryCache
[1]->asn
== asn
))
88 retval
= EntryCache
[1];
89 else if (EntryCache
[2] && vpn
== EntryCache
[2]->tag
&&
90 (EntryCache
[2]->asma
|| EntryCache
[2]->asn
== asn
))
91 retval
= EntryCache
[2];
96 PageTable::const_iterator i
= lookupTable
.find(vpn
);
97 if (i
!= lookupTable
.end()) {
98 while (i
->first
== vpn
) {
99 int index
= i
->second
;
100 TlbEntry
*entry
= &table
[index
];
101 assert(entry
->valid
);
102 if (vpn
== entry
->tag
&& (entry
->asma
|| entry
->asn
== asn
)) {
103 retval
= updateCache(entry
);
112 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
113 retval
? "hit" : "miss", retval
? retval
->ppn
: 0);
119 TLB::checkCacheability(RequestPtr
&req
)
121 // in Alpha, cacheability is controlled by upper-level bits of the
125 * We support having the uncacheable bit in either bit 39 or bit 40.
126 * The Turbolaser platform (and EV5) support having the bit in 39, but
127 * Tsunami (which Linux assumes uses an EV6) generates accesses with
128 * the bit in 40. So we must check for both, but we have debug flags
129 * to catch a weird case where both are used, which shouldn't happen.
134 if (req
->getPaddr() & PAddrUncachedBit39
)
136 if (req
->getPaddr() & PAddrUncachedBit43
)
139 // IPR memory space not implemented
140 if (PAddrIprSpace(req
->getPaddr())) {
141 return new UnimpFault("IPR memory space not implemented!");
143 // mark request as uncacheable
144 req
->setFlags(req
->getFlags() | UNCACHEABLE
);
147 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
148 req
->setPaddr(req
->getPaddr() & PAddrUncachedMask
);
156 // insert a new TLB entry
158 TLB::insert(Addr addr
, TlbEntry
&entry
)
162 if (table
[nlu
].valid
) {
163 Addr oldvpn
= table
[nlu
].tag
;
164 PageTable::iterator i
= lookupTable
.find(oldvpn
);
166 if (i
== lookupTable
.end())
167 panic("TLB entry not found in lookupTable");
170 while ((index
= i
->second
) != nlu
) {
171 if (table
[index
].tag
!= oldvpn
)
172 panic("TLB entry not found in lookupTable");
177 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
179 lookupTable
.erase(i
);
182 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vaddr
.vpn(), entry
.ppn
);
185 table
[nlu
].tag
= vaddr
.vpn();
186 table
[nlu
].valid
= true;
188 lookupTable
.insert(make_pair(vaddr
.vpn(), nlu
));
195 DPRINTF(TLB
, "flushAll\n");
196 memset(table
, 0, sizeof(TlbEntry
[size
]));
203 TLB::flushProcesses()
206 PageTable::iterator i
= lookupTable
.begin();
207 PageTable::iterator end
= lookupTable
.end();
209 int index
= i
->second
;
210 TlbEntry
*entry
= &table
[index
];
211 assert(entry
->valid
);
213 // we can't increment i after we erase it, so save a copy and
214 // increment it to get the next entry now
215 PageTable::iterator cur
= i
;
219 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, entry
->tag
, entry
->ppn
);
220 entry
->valid
= false;
221 lookupTable
.erase(cur
);
227 TLB::flushAddr(Addr addr
, uint8_t asn
)
232 PageTable::iterator i
= lookupTable
.find(vaddr
.vpn());
233 if (i
== lookupTable
.end())
236 while (i
!= lookupTable
.end() && i
->first
== vaddr
.vpn()) {
237 int index
= i
->second
;
238 TlbEntry
*entry
= &table
[index
];
239 assert(entry
->valid
);
241 if (vaddr
.vpn() == entry
->tag
&& (entry
->asma
|| entry
->asn
== asn
)) {
242 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vaddr
.vpn(),
245 // invalidate this entry
246 entry
->valid
= false;
248 lookupTable
.erase(i
++);
257 TLB::serialize(ostream
&os
)
259 SERIALIZE_SCALAR(size
);
260 SERIALIZE_SCALAR(nlu
);
262 for (int i
= 0; i
< size
; i
++) {
263 nameOut(os
, csprintf("%s.Entry%d", name(), i
));
264 table
[i
].serialize(os
);
269 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
271 UNSERIALIZE_SCALAR(size
);
272 UNSERIALIZE_SCALAR(nlu
);
274 for (int i
= 0; i
< size
; i
++) {
275 table
[i
].unserialize(cp
, csprintf("%s.Entry%d", section
, i
));
276 if (table
[i
].valid
) {
277 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
283 ///////////////////////////////////////////////////////////////////////
287 ITB::ITB(const Params
*p
)
296 .name(name() + ".hits")
299 .name(name() + ".misses")
302 .name(name() + ".acv")
305 .name(name() + ".accesses")
306 .desc("ITB accesses");
308 accesses
= hits
+ misses
;
313 ITB::translate(RequestPtr
&req
, ThreadContext
*tc
)
315 //If this is a pal pc, then set PHYSICAL
316 if(FULL_SYSTEM
&& PcPAL(req
->getPC()))
317 req
->setFlags(req
->getFlags() | PHYSICAL
);
319 if (PcPAL(req
->getPC())) {
320 // strip off PAL PC marker (lsb is 1)
321 req
->setPaddr((req
->getVaddr() & ~3) & PAddrImplMask
);
326 if (req
->getFlags() & PHYSICAL
) {
327 req
->setPaddr(req
->getVaddr());
329 // verify that this is a good virtual address
330 if (!validVirtualAddress(req
->getVaddr())) {
332 return new ItbAcvFault(req
->getVaddr());
336 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
337 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
339 if ((MCSR_SP(tc
->readMiscRegNoEffect(IPR_MCSR
)) & 2) &&
340 VAddrSpaceEV5(req
->getVaddr()) == 2)
342 if (VAddrSpaceEV6(req
->getVaddr()) == 0x7e)
345 // only valid in kernel mode
346 if (ICM_CM(tc
->readMiscRegNoEffect(IPR_ICM
)) !=
349 return new ItbAcvFault(req
->getVaddr());
352 req
->setPaddr(req
->getVaddr() & PAddrImplMask
);
355 // sign extend the physical address properly
356 if (req
->getPaddr() & PAddrUncachedBit40
)
357 req
->setPaddr(req
->getPaddr() | ULL(0xf0000000000));
359 req
->setPaddr(req
->getPaddr() & ULL(0xffffffffff));
363 // not a physical address: need to look up pte
364 int asn
= DTB_ASN_ASN(tc
->readMiscRegNoEffect(IPR_DTB_ASN
));
365 TlbEntry
*entry
= lookup(VAddr(req
->getVaddr()).vpn(),
370 return new ItbPageFault(req
->getVaddr());
373 req
->setPaddr((entry
->ppn
<< PageShift
) +
374 (VAddr(req
->getVaddr()).offset()
377 // check permissions for this access
379 (1 << ICM_CM(tc
->readMiscRegNoEffect(IPR_ICM
))))) {
380 // instruction access fault
382 return new ItbAcvFault(req
->getVaddr());
389 // check that the physical address is ok (catch bad physical addresses)
390 if (req
->getPaddr() & ~PAddrImplMask
)
391 return genMachineCheckFault();
393 return checkCacheability(req
);
397 ///////////////////////////////////////////////////////////////////////
401 DTB::DTB(const Params
*p
)
409 .name(name() + ".read_hits")
410 .desc("DTB read hits")
414 .name(name() + ".read_misses")
415 .desc("DTB read misses")
419 .name(name() + ".read_acv")
420 .desc("DTB read access violations")
424 .name(name() + ".read_accesses")
425 .desc("DTB read accesses")
429 .name(name() + ".write_hits")
430 .desc("DTB write hits")
434 .name(name() + ".write_misses")
435 .desc("DTB write misses")
439 .name(name() + ".write_acv")
440 .desc("DTB write access violations")
444 .name(name() + ".write_accesses")
445 .desc("DTB write accesses")
449 .name(name() + ".hits")
454 .name(name() + ".misses")
459 .name(name() + ".acv")
460 .desc("DTB access violations")
464 .name(name() + ".accesses")
465 .desc("DTB accesses")
468 hits
= read_hits
+ write_hits
;
469 misses
= read_misses
+ write_misses
;
470 acv
= read_acv
+ write_acv
;
471 accesses
= read_accesses
+ write_accesses
;
475 DTB::translate(RequestPtr
&req
, ThreadContext
*tc
, bool write
)
477 Addr pc
= tc
->readPC();
480 (mode_type
)DTB_CM_CM(tc
->readMiscRegNoEffect(IPR_DTB_CM
));
484 * Check for alignment faults
486 if (req
->getVaddr() & (req
->getSize() - 1)) {
487 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d", req
->getVaddr(),
489 uint64_t flags
= write
? MM_STAT_WR_MASK
: 0;
490 return new DtbAlignmentFault(req
->getVaddr(), req
->getFlags(), flags
);
494 mode
= (req
->getFlags() & ALTMODE
) ?
495 (mode_type
)ALT_MODE_AM(
496 tc
->readMiscRegNoEffect(IPR_ALT_MODE
))
500 if (req
->getFlags() & PHYSICAL
) {
501 req
->setPaddr(req
->getVaddr());
503 // verify that this is a good virtual address
504 if (!validVirtualAddress(req
->getVaddr())) {
505 if (write
) { write_acv
++; } else { read_acv
++; }
506 uint64_t flags
= (write
? MM_STAT_WR_MASK
: 0) |
507 MM_STAT_BAD_VA_MASK
|
509 return new DtbPageFault(req
->getVaddr(), req
->getFlags(), flags
);
512 // Check for "superpage" mapping
514 if ((MCSR_SP(tc
->readMiscRegNoEffect(IPR_MCSR
)) & 2) &&
515 VAddrSpaceEV5(req
->getVaddr()) == 2)
517 if (VAddrSpaceEV6(req
->getVaddr()) == 0x7e)
521 // only valid in kernel mode
522 if (DTB_CM_CM(tc
->readMiscRegNoEffect(IPR_DTB_CM
)) !=
524 if (write
) { write_acv
++; } else { read_acv
++; }
525 uint64_t flags
= ((write
? MM_STAT_WR_MASK
: 0) |
527 return new DtbAcvFault(req
->getVaddr(), req
->getFlags(), flags
);
530 req
->setPaddr(req
->getVaddr() & PAddrImplMask
);
533 // sign extend the physical address properly
534 if (req
->getPaddr() & PAddrUncachedBit40
)
535 req
->setPaddr(req
->getPaddr() | ULL(0xf0000000000));
537 req
->setPaddr(req
->getPaddr() & ULL(0xffffffffff));
546 int asn
= DTB_ASN_ASN(tc
->readMiscRegNoEffect(IPR_DTB_ASN
));
548 // not a physical address: need to look up pte
549 TlbEntry
*entry
= lookup(VAddr(req
->getVaddr()).vpn(), asn
);
553 if (write
) { write_misses
++; } else { read_misses
++; }
554 uint64_t flags
= (write
? MM_STAT_WR_MASK
: 0) |
555 MM_STAT_DTB_MISS_MASK
;
556 return (req
->getFlags() & VPTE
) ?
557 (Fault
)(new PDtbMissFault(req
->getVaddr(), req
->getFlags(),
559 (Fault
)(new NDtbMissFault(req
->getVaddr(), req
->getFlags(),
563 req
->setPaddr((entry
->ppn
<< PageShift
) +
564 VAddr(req
->getVaddr()).offset());
567 if (!(entry
->xwe
& MODE2MASK(mode
))) {
568 // declare the instruction access fault
570 uint64_t flags
= MM_STAT_WR_MASK
|
572 (entry
->fonw
? MM_STAT_FONW_MASK
: 0);
573 return new DtbPageFault(req
->getVaddr(), req
->getFlags(), flags
);
577 uint64_t flags
= MM_STAT_WR_MASK
|
579 return new DtbPageFault(req
->getVaddr(), req
->getFlags(), flags
);
582 if (!(entry
->xre
& MODE2MASK(mode
))) {
584 uint64_t flags
= MM_STAT_ACV_MASK
|
585 (entry
->fonr
? MM_STAT_FONR_MASK
: 0);
586 return new DtbAcvFault(req
->getVaddr(), req
->getFlags(), flags
);
590 uint64_t flags
= MM_STAT_FONR_MASK
;
591 return new DtbPageFault(req
->getVaddr(), req
->getFlags(), flags
);
602 // check that the physical address is ok (catch bad physical addresses)
603 if (req
->getPaddr() & ~PAddrImplMask
)
604 return genMachineCheckFault();
606 return checkCacheability(req
);
610 TLB::index(bool advance
)
612 TlbEntry
*entry
= &table
[nlu
];
620 /* end namespace AlphaISA */ }
623 AlphaITBParams::create()
625 return new AlphaISA::ITB(this);
629 AlphaDTBParams::create()
631 return new AlphaISA::DTB(this);