2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
36 #include "arch/alpha/faults.hh"
37 #include "arch/alpha/pagetable.hh"
38 #include "arch/alpha/tlb.hh"
39 #include "arch/generic/debugfaults.hh"
40 #include "base/inifile.hh"
41 #include "base/str.hh"
42 #include "base/trace.hh"
43 #include "cpu/thread_context.hh"
44 #include "debug/TLB.hh"
45 #include "sim/full_system.hh"
51 ///////////////////////////////////////////////////////////////////////
57 bool uncacheBit39
= false;
58 bool uncacheBit40
= false;
61 #define MODE2MASK(X) (1 << (X))
63 TLB::TLB(const Params
*p
)
64 : BaseTLB(p
), size(p
->size
), nlu(0)
66 table
= new TlbEntry
[size
];
67 memset(table
, 0, sizeof(TlbEntry
) * size
);
81 .name(name() + ".fetch_hits")
84 .name(name() + ".fetch_misses")
87 .name(name() + ".fetch_acv")
90 .name(name() + ".fetch_accesses")
91 .desc("ITB accesses");
93 fetch_accesses
= fetch_hits
+ fetch_misses
;
96 .name(name() + ".read_hits")
97 .desc("DTB read hits")
101 .name(name() + ".read_misses")
102 .desc("DTB read misses")
106 .name(name() + ".read_acv")
107 .desc("DTB read access violations")
111 .name(name() + ".read_accesses")
112 .desc("DTB read accesses")
116 .name(name() + ".write_hits")
117 .desc("DTB write hits")
121 .name(name() + ".write_misses")
122 .desc("DTB write misses")
126 .name(name() + ".write_acv")
127 .desc("DTB write access violations")
131 .name(name() + ".write_accesses")
132 .desc("DTB write accesses")
136 .name(name() + ".data_hits")
141 .name(name() + ".data_misses")
146 .name(name() + ".data_acv")
147 .desc("DTB access violations")
151 .name(name() + ".data_accesses")
152 .desc("DTB accesses")
155 data_hits
= read_hits
+ write_hits
;
156 data_misses
= read_misses
+ write_misses
;
157 data_acv
= read_acv
+ write_acv
;
158 data_accesses
= read_accesses
+ write_accesses
;
161 // look up an entry in the TLB
163 TLB::lookup(Addr vpn
, uint8_t asn
)
165 // assume not found...
166 TlbEntry
*retval
= NULL
;
169 if (vpn
== EntryCache
[0]->tag
&&
170 (EntryCache
[0]->asma
|| EntryCache
[0]->asn
== asn
))
171 retval
= EntryCache
[0];
172 else if (EntryCache
[1]) {
173 if (vpn
== EntryCache
[1]->tag
&&
174 (EntryCache
[1]->asma
|| EntryCache
[1]->asn
== asn
))
175 retval
= EntryCache
[1];
176 else if (EntryCache
[2] && vpn
== EntryCache
[2]->tag
&&
177 (EntryCache
[2]->asma
|| EntryCache
[2]->asn
== asn
))
178 retval
= EntryCache
[2];
182 if (retval
== NULL
) {
183 PageTable::const_iterator i
= lookupTable
.find(vpn
);
184 if (i
!= lookupTable
.end()) {
185 while (i
->first
== vpn
) {
186 int index
= i
->second
;
187 TlbEntry
*entry
= &table
[index
];
188 assert(entry
->valid
);
189 if (vpn
== entry
->tag
&& (entry
->asma
|| entry
->asn
== asn
)) {
190 retval
= updateCache(entry
);
199 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
200 retval
? "hit" : "miss", retval
? retval
->ppn
: 0);
205 TLB::checkCacheability(RequestPtr
&req
, bool itb
)
207 // in Alpha, cacheability is controlled by upper-level bits of the
211 * We support having the uncacheable bit in either bit 39 or bit
212 * 40. The Turbolaser platform (and EV5) support having the bit
213 * in 39, but Tsunami (which Linux assumes uses an EV6) generates
214 * accesses with the bit in 40. So we must check for both, but we
215 * have debug flags to catch a weird case where both are used,
216 * which shouldn't happen.
220 if (req
->getPaddr() & PAddrUncachedBit43
) {
221 // IPR memory space not implemented
222 if (PAddrIprSpace(req
->getPaddr())) {
223 return new UnimpFault("IPR memory space not implemented!");
225 // mark request as uncacheable
226 req
->setFlags(Request::UNCACHEABLE
);
228 // Clear bits 42:35 of the physical address (10-2 in
230 req
->setPaddr(req
->getPaddr() & PAddrUncachedMask
);
232 // We shouldn't be able to read from an uncachable address in Alpha as
233 // we don't have a ROM and we don't want to try to fetch from a device
234 // register as we destroy any data that is clear-on-read.
235 if (req
->isUncacheable() && itb
)
236 return new UnimpFault("CPU trying to fetch from uncached I/O");
243 // insert a new TLB entry
245 TLB::insert(Addr addr
, TlbEntry
&entry
)
249 if (table
[nlu
].valid
) {
250 Addr oldvpn
= table
[nlu
].tag
;
251 PageTable::iterator i
= lookupTable
.find(oldvpn
);
253 if (i
== lookupTable
.end())
254 panic("TLB entry not found in lookupTable");
257 while ((index
= i
->second
) != nlu
) {
258 if (table
[index
].tag
!= oldvpn
)
259 panic("TLB entry not found in lookupTable");
264 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
266 lookupTable
.erase(i
);
269 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vaddr
.vpn(), entry
.ppn
);
272 table
[nlu
].tag
= vaddr
.vpn();
273 table
[nlu
].valid
= true;
275 lookupTable
.insert(make_pair(vaddr
.vpn(), nlu
));
282 DPRINTF(TLB
, "flushAll\n");
283 memset(table
, 0, sizeof(TlbEntry
) * size
);
290 TLB::flushProcesses()
293 PageTable::iterator i
= lookupTable
.begin();
294 PageTable::iterator end
= lookupTable
.end();
296 int index
= i
->second
;
297 TlbEntry
*entry
= &table
[index
];
298 assert(entry
->valid
);
300 // we can't increment i after we erase it, so save a copy and
301 // increment it to get the next entry now
302 PageTable::iterator cur
= i
;
306 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
,
307 entry
->tag
, entry
->ppn
);
308 entry
->valid
= false;
309 lookupTable
.erase(cur
);
315 TLB::flushAddr(Addr addr
, uint8_t asn
)
320 PageTable::iterator i
= lookupTable
.find(vaddr
.vpn());
321 if (i
== lookupTable
.end())
324 while (i
!= lookupTable
.end() && i
->first
== vaddr
.vpn()) {
325 int index
= i
->second
;
326 TlbEntry
*entry
= &table
[index
];
327 assert(entry
->valid
);
329 if (vaddr
.vpn() == entry
->tag
&& (entry
->asma
|| entry
->asn
== asn
)) {
330 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vaddr
.vpn(),
333 // invalidate this entry
334 entry
->valid
= false;
336 lookupTable
.erase(i
++);
345 TLB::serialize(ostream
&os
)
347 SERIALIZE_SCALAR(size
);
348 SERIALIZE_SCALAR(nlu
);
350 for (int i
= 0; i
< size
; i
++) {
351 nameOut(os
, csprintf("%s.Entry%d", name(), i
));
352 table
[i
].serialize(os
);
357 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
359 UNSERIALIZE_SCALAR(size
);
360 UNSERIALIZE_SCALAR(nlu
);
362 for (int i
= 0; i
< size
; i
++) {
363 table
[i
].unserialize(cp
, csprintf("%s.Entry%d", section
, i
));
364 if (table
[i
].valid
) {
365 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
371 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
373 //If this is a pal pc, then set PHYSICAL
374 if (FullSystem
&& PcPAL(req
->getPC()))
375 req
->setFlags(Request::PHYSICAL
);
377 if (PcPAL(req
->getPC())) {
378 // strip off PAL PC marker (lsb is 1)
379 req
->setPaddr((req
->getVaddr() & ~3) & PAddrImplMask
);
384 if (req
->getFlags() & Request::PHYSICAL
) {
385 req
->setPaddr(req
->getVaddr());
387 // verify that this is a good virtual address
388 if (!validVirtualAddress(req
->getVaddr())) {
390 return new ItbAcvFault(req
->getVaddr());
394 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
395 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
396 if (VAddrSpaceEV6(req
->getVaddr()) == 0x7e) {
397 // only valid in kernel mode
398 if (ICM_CM(tc
->readMiscRegNoEffect(IPR_ICM
)) !=
401 return new ItbAcvFault(req
->getVaddr());
404 req
->setPaddr(req
->getVaddr() & PAddrImplMask
);
406 // sign extend the physical address properly
407 if (req
->getPaddr() & PAddrUncachedBit40
)
408 req
->setPaddr(req
->getPaddr() | ULL(0xf0000000000));
410 req
->setPaddr(req
->getPaddr() & ULL(0xffffffffff));
412 // not a physical address: need to look up pte
413 int asn
= DTB_ASN_ASN(tc
->readMiscRegNoEffect(IPR_DTB_ASN
));
414 TlbEntry
*entry
= lookup(VAddr(req
->getVaddr()).vpn(),
419 return new ItbPageFault(req
->getVaddr());
422 req
->setPaddr((entry
->ppn
<< PageShift
) +
423 (VAddr(req
->getVaddr()).offset()
426 // check permissions for this access
428 (1 << ICM_CM(tc
->readMiscRegNoEffect(IPR_ICM
))))) {
429 // instruction access fault
431 return new ItbAcvFault(req
->getVaddr());
438 // check that the physical address is ok (catch bad physical addresses)
439 if (req
->getPaddr() & ~PAddrImplMask
) {
440 return new MachineCheckFault();
443 return checkCacheability(req
, true);
448 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
451 (mode_type
)DTB_CM_CM(tc
->readMiscRegNoEffect(IPR_DTB_CM
));
454 * Check for alignment faults
456 if (req
->getVaddr() & (req
->getSize() - 1)) {
457 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d\n", req
->getVaddr(),
459 uint64_t flags
= write
? MM_STAT_WR_MASK
: 0;
460 return new DtbAlignmentFault(req
->getVaddr(), req
->getFlags(), flags
);
463 if (PcPAL(req
->getPC())) {
464 mode
= (req
->getFlags() & Request::ALTMODE
) ?
465 (mode_type
)ALT_MODE_AM(
466 tc
->readMiscRegNoEffect(IPR_ALT_MODE
))
470 if (req
->getFlags() & Request::PHYSICAL
) {
471 req
->setPaddr(req
->getVaddr());
473 // verify that this is a good virtual address
474 if (!validVirtualAddress(req
->getVaddr())) {
475 if (write
) { write_acv
++; } else { read_acv
++; }
476 uint64_t flags
= (write
? MM_STAT_WR_MASK
: 0) |
477 MM_STAT_BAD_VA_MASK
|
479 return new DtbPageFault(req
->getVaddr(), req
->getFlags(), flags
);
482 // Check for "superpage" mapping
483 if (VAddrSpaceEV6(req
->getVaddr()) == 0x7e) {
484 // only valid in kernel mode
485 if (DTB_CM_CM(tc
->readMiscRegNoEffect(IPR_DTB_CM
)) !=
487 if (write
) { write_acv
++; } else { read_acv
++; }
488 uint64_t flags
= ((write
? MM_STAT_WR_MASK
: 0) |
491 return new DtbAcvFault(req
->getVaddr(), req
->getFlags(),
495 req
->setPaddr(req
->getVaddr() & PAddrImplMask
);
497 // sign extend the physical address properly
498 if (req
->getPaddr() & PAddrUncachedBit40
)
499 req
->setPaddr(req
->getPaddr() | ULL(0xf0000000000));
501 req
->setPaddr(req
->getPaddr() & ULL(0xffffffffff));
508 int asn
= DTB_ASN_ASN(tc
->readMiscRegNoEffect(IPR_DTB_ASN
));
510 // not a physical address: need to look up pte
511 TlbEntry
*entry
= lookup(VAddr(req
->getVaddr()).vpn(), asn
);
515 if (write
) { write_misses
++; } else { read_misses
++; }
516 uint64_t flags
= (write
? MM_STAT_WR_MASK
: 0) |
517 MM_STAT_DTB_MISS_MASK
;
518 return (req
->getFlags() & Request::VPTE
) ?
519 (Fault
)(new PDtbMissFault(req
->getVaddr(), req
->getFlags(),
521 (Fault
)(new NDtbMissFault(req
->getVaddr(), req
->getFlags(),
525 req
->setPaddr((entry
->ppn
<< PageShift
) +
526 VAddr(req
->getVaddr()).offset());
529 if (!(entry
->xwe
& MODE2MASK(mode
))) {
530 // declare the instruction access fault
532 uint64_t flags
= MM_STAT_WR_MASK
|
534 (entry
->fonw
? MM_STAT_FONW_MASK
: 0);
535 return new DtbPageFault(req
->getVaddr(), req
->getFlags(),
540 uint64_t flags
= MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
;
541 return new DtbPageFault(req
->getVaddr(), req
->getFlags(),
545 if (!(entry
->xre
& MODE2MASK(mode
))) {
547 uint64_t flags
= MM_STAT_ACV_MASK
|
548 (entry
->fonr
? MM_STAT_FONR_MASK
: 0);
549 return new DtbAcvFault(req
->getVaddr(), req
->getFlags(),
554 uint64_t flags
= MM_STAT_FONR_MASK
;
555 return new DtbPageFault(req
->getVaddr(), req
->getFlags(),
567 // check that the physical address is ok (catch bad physical addresses)
568 if (req
->getPaddr() & ~PAddrImplMask
) {
569 return new MachineCheckFault();
572 return checkCacheability(req
);
576 TLB::index(bool advance
)
578 TlbEntry
*entry
= &table
[nlu
];
587 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
590 return translateInst(req
, tc
);
592 return translateData(req
, tc
, mode
== Write
);
596 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
597 Translation
*translation
, Mode mode
)
600 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
604 TLB::translateFunctional(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
606 panic("Not implemented\n");
611 TLB::finalizePhysical(RequestPtr req
, ThreadContext
*tc
, Mode mode
) const
616 } // namespace AlphaISA
619 AlphaTLBParams::create()
621 return new AlphaISA::TLB(this);