src/arch/alpha/tlb.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Nathan Binkert
  29  *          Steve Reinhardt
  30  */
  31
  32 #ifndef __ARCH_ALPHA_TLB_HH__
  33 #define __ARCH_ALPHA_TLB_HH__
  34
  35 #include <map>
  36
  37 #include "arch/alpha/ev5.hh"
  38 #include "arch/alpha/isa_traits.hh"
  39 #include "arch/alpha/pagetable.hh"
  40 #include "arch/alpha/utility.hh"
  41 #include "arch/alpha/vtophys.hh"
  42 #include "base/statistics.hh"
  43 #include "mem/request.hh"
  44 #include "params/AlphaTLB.hh"
  45 #include "sim/fault_fwd.hh"
  46 #include "sim/tlb.hh"
  47
  48 class ThreadContext;
  49
  50 namespace AlphaISA {
  51
  52 struct TlbEntry;
  53
  54 class TLB : public BaseTLB
  55 {
  56   protected:
  57     mutable Stats::Scalar fetch_hits;
  58     mutable Stats::Scalar fetch_misses;
  59     mutable Stats::Scalar fetch_acv;
  60     mutable Stats::Formula fetch_accesses;
  61     mutable Stats::Scalar read_hits;
  62     mutable Stats::Scalar read_misses;
  63     mutable Stats::Scalar read_acv;
  64     mutable Stats::Scalar read_accesses;
  65     mutable Stats::Scalar write_hits;
  66     mutable Stats::Scalar write_misses;
  67     mutable Stats::Scalar write_acv;
  68     mutable Stats::Scalar write_accesses;
  69     Stats::Formula data_hits;
  70     Stats::Formula data_misses;
  71     Stats::Formula data_acv;
  72     Stats::Formula data_accesses;
  73
  74
  75     typedef std::multimap<Addr, int> PageTable;
  76     PageTable lookupTable;  // Quick lookup into page table
  77
  78     TlbEntry *table;        // the Page Table
  79     int size;               // TLB Size
  80     int nlu;                // not last used entry (for replacement)
  81
  82     void nextnlu() { if (++nlu >= size) nlu = 0; }
  83     TlbEntry *lookup(Addr vpn, uint8_t asn);
  84
  85   public:
  86     typedef AlphaTLBParams Params;
  87     TLB(const Params *p);
  88     virtual ~TLB();
  89
  90     void takeOverFrom(BaseTLB *otlb) {}
  91
  92     virtual void regStats();
  93
  94     int getsize() const { return size; }
  95
  96     TlbEntry &index(bool advance = true);
  97     void insert(Addr vaddr, TlbEntry &entry);
  98
  99     void flushAll();
 100     void flushProcesses();
 101     void flushAddr(Addr addr, uint8_t asn);
 102
 103     void
 104     demapPage(Addr vaddr, uint64_t asn)
 105     {
 106         assert(asn < (1 << 8));
 107         flushAddr(vaddr, asn);
 108     }
 109
 110     // static helper functions... really EV5 VM traits
 111     static bool
 112     validVirtualAddress(Addr vaddr)
 113     {
 114         // unimplemented bits must be all 0 or all 1
 115         Addr unimplBits = vaddr & VAddrUnImplMask;
 116         return unimplBits == 0 || unimplBits == VAddrUnImplMask;
 117     }
 118
 119     static Fault checkCacheability(RequestPtr &req, bool itb = false);
 120
 121     // Checkpointing
 122     virtual void serialize(std::ostream &os);
 123     virtual void unserialize(Checkpoint *cp, const std::string &section);
 124
 125     // Most recently used page table entries
 126     TlbEntry *EntryCache[3];
 127     inline void
 128     flushCache()
 129     {
 130         memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
 131     }
 132
 133     inline TlbEntry *
 134     updateCache(TlbEntry *entry) {
 135         EntryCache[2] = EntryCache[1];
 136         EntryCache[1] = EntryCache[0];
 137         EntryCache[0] = entry;
 138         return entry;
 139     }
 140
 141   protected:
 142     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 143     Fault translateInst(RequestPtr req, ThreadContext *tc);
 144
 145   public:
 146     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 147     void translateTiming(RequestPtr req, ThreadContext *tc,
 148                          Translation *translation, Mode mode);
 149     /**
 150      * translateFunctional stub function for future CheckerCPU support
 151      */
 152     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 153     Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
 154 };
 155
 156 } // namespace AlphaISA
 157
 158 #endif // __ARCH_ALPHA_TLB_HH__