2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
32 #ifndef __ARCH_ALPHA_TLB_HH__
33 #define __ARCH_ALPHA_TLB_HH__
37 #include "arch/alpha/ev5.hh"
38 #include "arch/alpha/isa_traits.hh"
39 #include "arch/alpha/pagetable.hh"
40 #include "arch/alpha/utility.hh"
41 #include "arch/alpha/vtophys.hh"
42 #include "base/statistics.hh"
43 #include "mem/request.hh"
44 #include "params/AlphaDTB.hh"
45 #include "params/AlphaITB.hh"
46 #include "sim/faults.hh"
55 class TLB : public BaseTLB
58 typedef std::multimap<Addr, int> PageTable;
59 PageTable lookupTable; // Quick lookup into page table
61 TlbEntry *table; // the Page Table
63 int nlu; // not last used entry (for replacement)
65 void nextnlu() { if (++nlu >= size) nlu = 0; }
66 TlbEntry *lookup(Addr vpn, uint8_t asn);
69 typedef AlphaTLBParams Params;
73 int getsize() const { return size; }
75 TlbEntry &index(bool advance = true);
76 void insert(Addr vaddr, TlbEntry &entry);
79 void flushProcesses();
80 void flushAddr(Addr addr, uint8_t asn);
83 demapPage(Addr vaddr, uint64_t asn)
85 assert(asn < (1 << 8));
86 flushAddr(vaddr, asn);
89 // static helper functions... really EV5 VM traits
91 validVirtualAddress(Addr vaddr)
93 // unimplemented bits must be all 0 or all 1
94 Addr unimplBits = vaddr & VAddrUnImplMask;
95 return unimplBits == 0 || unimplBits == VAddrUnImplMask;
98 static Fault checkCacheability(RequestPtr &req, bool itb = false);
101 virtual void serialize(std::ostream &os);
102 virtual void unserialize(Checkpoint *cp, const std::string §ion);
104 // Most recently used page table entries
105 TlbEntry *EntryCache[3];
109 memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
113 updateCache(TlbEntry *entry) {
114 EntryCache[2] = EntryCache[1];
115 EntryCache[1] = EntryCache[0];
116 EntryCache[0] = entry;
121 class ITB : public TLB
124 mutable Stats::Scalar<> hits;
125 mutable Stats::Scalar<> misses;
126 mutable Stats::Scalar<> acv;
127 mutable Stats::Formula accesses;
130 typedef AlphaITBParams Params;
131 ITB(const Params *p);
132 virtual void regStats();
134 Fault translate(RequestPtr &req, ThreadContext *tc);
137 class DTB : public TLB
140 mutable Stats::Scalar<> read_hits;
141 mutable Stats::Scalar<> read_misses;
142 mutable Stats::Scalar<> read_acv;
143 mutable Stats::Scalar<> read_accesses;
144 mutable Stats::Scalar<> write_hits;
145 mutable Stats::Scalar<> write_misses;
146 mutable Stats::Scalar<> write_acv;
147 mutable Stats::Scalar<> write_accesses;
149 Stats::Formula misses;
151 Stats::Formula accesses;
154 typedef AlphaDTBParams Params;
155 DTB(const Params *p);
156 virtual void regStats();
158 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
161 } // namespace AlphaISA
163 #endif // __ARCH_ALPHA_TLB_HH__