src/arch/alpha/tlb.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Nathan Binkert
  29  *          Steve Reinhardt
  30  */
  31
  32 #ifndef __ALPHA_MEMORY_HH__
  33 #define __ALPHA_MEMORY_HH__
  34
  35 #include <map>
  36
  37 #include "arch/alpha/ev5.hh"
  38 #include "arch/alpha/isa_traits.hh"
  39 #include "arch/alpha/faults.hh"
  40 #include "base/statistics.hh"
  41 #include "mem/request.hh"
  42 #include "sim/sim_object.hh"
  43
  44 class ThreadContext;
  45
  46 class AlphaTLB : public SimObject
  47 {
  48   protected:
  49     typedef std::multimap<Addr, int> PageTable;
  50     PageTable lookupTable;      // Quick lookup into page table
  51
  52     AlphaISA::PTE *table;       // the Page Table
  53     int size;                   // TLB Size
  54     int nlu;                    // not last used entry (for replacement)
  55
  56     void nextnlu() { if (++nlu >= size) nlu = 0; }
  57     AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
  58
  59   public:
  60     AlphaTLB(const std::string &name, int size);
  61     virtual ~AlphaTLB();
  62
  63     int getsize() const { return size; }
  64
  65     AlphaISA::PTE &index(bool advance = true);
  66     void insert(Addr vaddr, AlphaISA::PTE &pte);
  67
  68     void flushAll();
  69     void flushProcesses();
  70     void flushAddr(Addr addr, uint8_t asn);
  71
  72     // static helper functions... really EV5 VM traits
  73     static bool validVirtualAddress(Addr vaddr) {
  74         // unimplemented bits must be all 0 or all 1
  75         Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
  76         return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
  77     }
  78
  79     static Fault checkCacheability(RequestPtr &req);
  80
  81     // Checkpointing
  82     virtual void serialize(std::ostream &os);
  83     virtual void unserialize(Checkpoint *cp, const std::string &section);
  84 };
  85
  86 class AlphaITB : public AlphaTLB
  87 {
  88   protected:
  89     mutable Stats::Scalar<> hits;
  90     mutable Stats::Scalar<> misses;
  91     mutable Stats::Scalar<> acv;
  92     mutable Stats::Formula accesses;
  93
  94   public:
  95     AlphaITB(const std::string &name, int size);
  96     virtual void regStats();
  97
  98     Fault translate(RequestPtr &req, ThreadContext *tc) const;
  99 };
 100
 101 class AlphaDTB : public AlphaTLB
 102 {
 103   protected:
 104     mutable Stats::Scalar<> read_hits;
 105     mutable Stats::Scalar<> read_misses;
 106     mutable Stats::Scalar<> read_acv;
 107     mutable Stats::Scalar<> read_accesses;
 108     mutable Stats::Scalar<> write_hits;
 109     mutable Stats::Scalar<> write_misses;
 110     mutable Stats::Scalar<> write_acv;
 111     mutable Stats::Scalar<> write_accesses;
 112     Stats::Formula hits;
 113     Stats::Formula misses;
 114     Stats::Formula acv;
 115     Stats::Formula accesses;
 116
 117   public:
 118     AlphaDTB(const std::string &name, int size);
 119     virtual void regStats();
 120
 121     Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
 122 };
 123
 124 #endif // __ALPHA_MEMORY_HH__