src/arch/alpha/utility.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Nathan Binkert
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/alpha/utility.hh"
  33 #include "arch/alpha/vtophys.hh"
  34 #include "mem/fs_translating_port_proxy.hh"
  35 #include "sim/full_system.hh"
  36
  37 namespace AlphaISA {
  38
  39 uint64_t
  40 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  41 {
  42     if (FullSystem) {
  43         const int NumArgumentRegs = 6;
  44         if (number < NumArgumentRegs) {
  45             if (fp)
  46                 return tc->readFloatRegBits(16 + number);
  47             else
  48                 return tc->readIntReg(16 + number);
  49         } else {
  50             Addr sp = tc->readIntReg(StackPointerReg);
  51             FSTranslatingPortProxy* vp = tc->getVirtProxy();
  52             uint64_t arg = vp->read<uint64_t>(sp +
  53                                (number-NumArgumentRegs) * sizeof(uint64_t));
  54             return arg;
  55         }
  56     } else {
  57         panic("getArgument() is Full system only\n");
  58         M5_DUMMY_RETURN;
  59     }
  60 }
  61
  62 void
  63 copyRegs(ThreadContext *src, ThreadContext *dest)
  64 {
  65     // First loop through the integer registers.
  66     for (int i = 0; i < NumIntRegs; ++i)
  67         dest->setIntReg(i, src->readIntReg(i));
  68
  69     // Then loop through the floating point registers.
  70     for (int i = 0; i < NumFloatRegs; ++i)
  71         dest->setFloatRegBits(i, src->readFloatRegBits(i));
  72
  73     // Copy misc. registers
  74     copyMiscRegs(src, dest);
  75
  76     // Lastly copy PC/NPC
  77     dest->pcState(src->pcState());
  78 }
  79
  80 void
  81 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
  82 {
  83     dest->setMiscRegNoEffect(MISCREG_FPCR,
  84         src->readMiscRegNoEffect(MISCREG_FPCR));
  85     dest->setMiscRegNoEffect(MISCREG_UNIQ,
  86         src->readMiscRegNoEffect(MISCREG_UNIQ));
  87     dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
  88         src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
  89     dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
  90         src->readMiscRegNoEffect(MISCREG_LOCKADDR));
  91
  92     copyIprs(src, dest);
  93 }
  94
  95 void
  96 skipFunction(ThreadContext *tc)
  97 {
  98     TheISA::PCState newPC = tc->pcState();
  99     newPC.set(tc->readIntReg(ReturnAddressReg));
 100     tc->pcState(newPC);
 101 }
 102
 103
 104 } // namespace AlphaISA
 105