src/arch/alpha/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Nathan Binkert
  29  *          Steve Reinhardt
  30  */
  31
  32 #ifndef __ARCH_ALPHA_UTILITY_HH__
  33 #define __ARCH_ALPHA_UTILITY_HH__
  34
  35 #include "config/full_system.hh"
  36 #include "arch/alpha/types.hh"
  37 #include "arch/alpha/isa_traits.hh"
  38 #include "arch/alpha/regfile.hh"
  39 #include "base/misc.hh"
  40 #include "cpu/thread_context.hh"
  41
  42 namespace AlphaISA
  43 {
  44
  45     static inline bool
  46     inUserMode(ThreadContext *tc)
  47     {
  48         return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
  49     }
  50
  51     static inline ExtMachInst
  52     makeExtMI(MachInst inst, Addr pc) {
  53 #if FULL_SYSTEM
  54         ExtMachInst ext_inst = inst;
  55         if (pc && 0x1)
  56             return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
  57         else
  58             return ext_inst;
  59 #else
  60         return ExtMachInst(inst);
  61 #endif
  62     }
  63
  64     inline bool isCallerSaveIntegerRegister(unsigned int reg) {
  65         panic("register classification not implemented");
  66         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
  67     }
  68
  69     inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
  70         panic("register classification not implemented");
  71         return (reg >= 9 && reg <= 15);
  72     }
  73
  74     inline bool isCallerSaveFloatRegister(unsigned int reg) {
  75         panic("register classification not implemented");
  76         return false;
  77     }
  78
  79     inline bool isCalleeSaveFloatRegister(unsigned int reg) {
  80         panic("register classification not implemented");
  81         return false;
  82     }
  83
  84     inline Addr alignAddress(const Addr &addr,
  85                                          unsigned int nbytes) {
  86         return (addr & ~(nbytes - 1));
  87     }
  88
  89     // Instruction address compression hooks
  90     inline Addr realPCToFetchPC(const Addr &addr) {
  91         return addr;
  92     }
  93
  94     inline Addr fetchPCToRealPC(const Addr &addr) {
  95         return addr;
  96     }
  97
  98     // the size of "fetched" instructions (not necessarily the size
  99     // of real instructions for PISA)
 100     inline size_t fetchInstSize() {
 101         return sizeof(MachInst);
 102     }
 103
 104     inline MachInst makeRegisterCopy(int dest, int src) {
 105         panic("makeRegisterCopy not implemented");
 106         return 0;
 107     }
 108
 109     // Machine operations
 110
 111     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 112                                int regnum);
 113
 114     void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 115                                   int regnum);
 116
 117     /**
 118      * Function to insure ISA semantics about 0 registers.
 119      * @param tc The thread context.
 120      */
 121     template <class TC>
 122     void zeroRegisters(TC *tc);
 123
 124     // Alpha IPR register accessors
 125     inline bool PcPAL(Addr addr) { return addr & 0x3; }
 126 #if FULL_SYSTEM
 127
 128     ////////////////////////////////////////////////////////////////////////
 129     //
 130     //  Translation stuff
 131     //
 132
 133     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 134
 135     // User Virtual
 136     inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
 137
 138     // Kernel Direct Mapped
 139     inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
 140     inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
 141
 142     // Kernel Virtual
 143     inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
 144
 145     inline Addr
 146     TruncPage(Addr addr)
 147     { return addr & ~(PageBytes - 1); }
 148
 149     inline Addr
 150     RoundPage(Addr addr)
 151     { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 152
 153     void initCPU(ThreadContext *tc, int cpuId);
 154     void initIPRs(ThreadContext *tc, int cpuId);
 155
 156     /**
 157      * Function to check for and process any interrupts.
 158      * @param tc The thread context.
 159      */
 160     template <class TC>
 161     void processInterrupts(TC *tc);
 162 #endif
 163
 164 } // namespace AlphaISA
 165
 166 #endif