2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
32 #ifndef __ARCH_ALPHA_UTILITY_HH__
33 #define __ARCH_ALPHA_UTILITY_HH__
35 #include "config/full_system.hh"
36 #include "arch/alpha/types.hh"
37 #include "arch/alpha/isa_traits.hh"
38 #include "arch/alpha/regfile.hh"
39 #include "base/misc.hh"
40 #include "cpu/thread_context.hh"
46 inUserMode(ThreadContext *tc)
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
51 static inline ExtMachInst
52 makeExtMI(MachInst inst, Addr pc) {
54 ExtMachInst ext_inst = inst;
56 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
60 return ExtMachInst(inst);
64 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
65 panic("register classification not implemented");
66 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
69 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
70 panic("register classification not implemented");
71 return (reg >= 9 && reg <= 15);
74 inline bool isCallerSaveFloatRegister(unsigned int reg) {
75 panic("register classification not implemented");
79 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
80 panic("register classification not implemented");
84 inline Addr alignAddress(const Addr &addr,
85 unsigned int nbytes) {
86 return (addr & ~(nbytes - 1));
89 // Instruction address compression hooks
90 inline Addr realPCToFetchPC(const Addr &addr) {
94 inline Addr fetchPCToRealPC(const Addr &addr) {
98 // the size of "fetched" instructions (not necessarily the size
99 // of real instructions for PISA)
100 inline size_t fetchInstSize() {
101 return sizeof(MachInst);
104 inline MachInst makeRegisterCopy(int dest, int src) {
105 panic("makeRegisterCopy not implemented");
109 // Machine operations
111 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
114 void restoreMachineReg(RegFile ®s, const AnyReg ®,
118 * Function to insure ISA semantics about 0 registers.
119 * @param tc The thread context.
122 void zeroRegisters(TC *tc);
124 // Alpha IPR register accessors
125 inline bool PcPAL(Addr addr) { return addr & 0x3; }
128 ////////////////////////////////////////////////////////////////////////
133 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
136 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
138 // Kernel Direct Mapped
139 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
140 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
143 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
147 { return addr & ~(PageBytes - 1); }
151 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
153 void initCPU(ThreadContext *tc, int cpuId);
154 void initIPRs(ThreadContext *tc, int cpuId);
157 * Function to check for and process any interrupts.
158 * @param tc The thread context.
161 void processInterrupts(TC *tc);
164 } // namespace AlphaISA