2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
32 #ifndef __ARCH_ALPHA_UTILITY_HH__
33 #define __ARCH_ALPHA_UTILITY_HH__
35 #include "arch/alpha/isa_traits.hh"
36 #include "arch/alpha/registers.hh"
37 #include "arch/alpha/types.hh"
38 #include "base/misc.hh"
39 #include "config/full_system.hh"
40 #include "cpu/static_inst.hh"
41 #include "cpu/thread_context.hh"
42 #include "arch/alpha/ev5.hh"
47 buildRetPC(const PCState &curPC, const PCState &callPC)
49 PCState retPC = callPC;
54 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
57 inUserMode(ThreadContext *tc)
59 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
63 * Function to insure ISA semantics about 0 registers.
64 * @param tc The thread context.
67 void zeroRegisters(TC *tc);
69 // Alpha IPR register accessors
70 inline bool PcPAL(Addr addr) { return addr & 0x3; }
71 inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
73 ////////////////////////////////////////////////////////////////////////
78 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
81 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
83 // Kernel Direct Mapped
84 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
85 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
88 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
92 { return addr & ~(PageBytes - 1); }
96 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
98 void initIPRs(ThreadContext *tc, int cpuId);
100 void initCPU(ThreadContext *tc, int cpuId);
103 void copyRegs(ThreadContext *src, ThreadContext *dest);
105 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
107 void skipFunction(ThreadContext *tc);
110 advancePC(PCState &pc, const StaticInstPtr inst)
116 getExecutingAsid(ThreadContext *tc)
118 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
121 } // namespace AlphaISA
123 #endif // __ARCH_ALPHA_UTILITY_HH__