2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
32 #ifndef __ARCH_ALPHA_UTILITY_HH__
33 #define __ARCH_ALPHA_UTILITY_HH__
35 #include "config/full_system.hh"
36 #include "arch/alpha/types.hh"
37 #include "arch/alpha/constants.hh"
38 #include "arch/alpha/regfile.hh"
39 #include "base/misc.hh"
44 static inline ExtMachInst
45 makeExtMI(MachInst inst, const uint64_t &pc) {
47 ExtMachInst ext_inst = inst;
49 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
53 return ExtMachInst(inst);
57 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
58 panic("register classification not implemented");
59 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
62 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
63 panic("register classification not implemented");
64 return (reg >= 9 && reg <= 15);
67 inline bool isCallerSaveFloatRegister(unsigned int reg) {
68 panic("register classification not implemented");
72 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
73 panic("register classification not implemented");
77 inline Addr alignAddress(const Addr &addr,
78 unsigned int nbytes) {
79 return (addr & ~(nbytes - 1));
82 // Instruction address compression hooks
83 inline Addr realPCToFetchPC(const Addr &addr) {
87 inline Addr fetchPCToRealPC(const Addr &addr) {
91 // the size of "fetched" instructions (not necessarily the size
92 // of real instructions for PISA)
93 inline size_t fetchInstSize() {
94 return sizeof(MachInst);
97 inline MachInst makeRegisterCopy(int dest, int src) {
98 panic("makeRegisterCopy not implemented");
102 // Machine operations
104 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
107 void restoreMachineReg(RegFile ®s, const AnyReg ®,
111 * Function to insure ISA semantics about 0 registers.
112 * @param xc The execution context.
115 void zeroRegisters(XC *xc);
118 // Alpha IPR register accessors
119 inline bool PcPAL(Addr addr) { return addr & 0x1; }
121 ////////////////////////////////////////////////////////////////////////
126 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
129 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
131 // Kernel Direct Mapped
132 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
133 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
136 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
140 { return addr & ~(PageBytes - 1); }
144 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
146 void initCPU(ExecContext *xc, int cpuId);
147 void initIPRs(ExecContext *xc, int cpuId);
150 * Function to check for and process any interrupts.
151 * @param xc The execution context.
154 void processInterrupts(XC *xc);
157 } // namespace AlphaISA