src/arch/arm/ArmISA.py

   1 # Copyright (c) 2012-2013, 2015-2021 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
  17 # redistributions in binary form must reproduce the above copyright
  18 # notice, this list of conditions and the following disclaimer in the
  19 # documentation and/or other materials provided with the distribution;
  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35
  36 from m5.params import *
  37 from m5.proxy import *
  38
  39 from m5.objects.ArmPMU import ArmPMU
  40 from m5.objects.ArmSystem import SveVectorLength
  41 from m5.objects.BaseISA import BaseISA
  42 from m5.objects.ISACommon import VecRegRenameMode
  43
  44 # Enum for DecoderFlavor
  45 class DecoderFlavor(Enum): vals = ['Generic']
  46
  47 class ArmISA(BaseISA):
  48     type = 'ArmISA'
  49     cxx_class = 'ArmISA::ISA'
  50     cxx_header = "arch/arm/isa.hh"
  51
  52     system = Param.System(Parent.any, "System this ISA object belongs to")
  53
  54     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  55     decoderFlavor = Param.DecoderFlavor(
  56             'Generic', "Decoder flavor specification")
  57
  58     # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
  59     # When 'highest_el_is_64' (AArch64 support) is:
  60     #   True  -> Cortex-A57 TRM r0p0 MIDR is used
  61     #   False -> Cortex-A15 TRM r0p0 MIDR is used
  62     midr = Param.UInt32(0x0, "MIDR value")
  63
  64     # See section B4.1.89 - B4.1.92 of the ARM ARM
  65     #  VMSAv7 support
  66     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  67     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  68     # no HW access | WFI stalling | ISB and DSB |
  69     # all TLB maintenance | no Harvard
  70     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  71     # SuperSec | Coherent TLB | Bcast Maint |
  72     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  73     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  74
  75     # See section B4.1.84 of ARM ARM
  76     # All values are latest for ARMv7-A profile
  77     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  78     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  79     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  80     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  81     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  82     id_isar5 = Param.UInt32(0x10000000, "Instruction Set Attribute Register 5")
  83
  84     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  85
  86     # [31:0] is implementation defined
  87     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  88         "AArch64 Auxiliary Feature Register 0")
  89     # Reserved for future expansion
  90     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  91         "AArch64 Auxiliary Feature Register 1")
  92
  93     # 1 CTX CMPs | 16 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
  94     id_aa64dfr0_el1 = Param.UInt64(0x0000000000F0F006,
  95         "AArch64 Debug Feature Register 0")
  96     # Reserved for future expansion
  97     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
  98         "AArch64 Debug Feature Register 1")
  99
 100     # !TME | !Atomic | !CRC32 | !SHA2 | !SHA1 | !AES
 101     id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
 102         "AArch64 Instruction Set Attribute Register 0")
 103
 104     # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
 105     id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
 106         "AArch64 Instruction Set Attribute Register 1")
 107
 108     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 109     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 110         "AArch64 Memory Model Feature Register 0")
 111     # PAN | HPDS | !VHE
 112     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
 113         "AArch64 Memory Model Feature Register 1")
 114     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 115         "AArch64 Memory Model Feature Register 2")
 116
 117     # Any access (read/write) to an unimplemented
 118     # Implementation Defined registers is not causing an Undefined Instruction.
 119     # It is rather executed as a NOP.
 120     impdef_nop = Param.Bool(False,
 121         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
 122
 123     # This is required because in SE mode a generic System SimObject is
 124     # allocated, instead of an ArmSystem
 125     sve_vl_se = Param.SveVectorLength(1,
 126         "SVE vector length in quadwords (128-bit), SE-mode only")