src/arch/arm/ArmISA.py

   1 # Copyright (c) 2012-2013, 2015-2021 ARM Limited
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  35
  36 from m5.params import *
  37 from m5.proxy import *
  38
  39 from m5.SimObject import SimObject
  40 from m5.objects.ArmPMU import ArmPMU
  41 from m5.objects.ArmSystem import SveVectorLength
  42 from m5.objects.BaseISA import BaseISA
  43 from m5.objects.ISACommon import VecRegRenameMode
  44
  45 # Enum for DecoderFlavor
  46 class DecoderFlavor(Enum): vals = ['Generic']
  47
  48 class ArmISA(BaseISA):
  49     type = 'ArmISA'
  50     cxx_class = 'ArmISA::ISA'
  51     cxx_header = "arch/arm/isa.hh"
  52
  53     system = Param.System(Parent.any, "System this ISA object belongs to")
  54
  55     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  56     decoderFlavor = Param.DecoderFlavor(
  57             'Generic', "Decoder flavor specification")
  58
  59     # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
  60     # When 'highest_el_is_64' (AArch64 support) is:
  61     #   True  -> Cortex-A57 TRM r0p0 MIDR is used
  62     #   False -> Cortex-A15 TRM r0p0 MIDR is used
  63     midr = Param.UInt32(0x0, "MIDR value")
  64
  65     # See section B4.1.89 - B4.1.92 of the ARM ARM
  66     #  VMSAv7 support
  67     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  68     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  69     # no HW access | WFI stalling | ISB and DSB |
  70     # all TLB maintenance | no Harvard
  71     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  72     # SuperSec | Coherent TLB | Bcast Maint |
  73     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  74     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  75     id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4")
  76
  77     # See section B4.1.84 of ARM ARM
  78     # All values are latest for ARMv7-A profile
  79     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  80     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  81     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  82     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  83     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  84     id_isar5 = Param.UInt32(0x11000000, "Instruction Set Attribute Register 5")
  85     # !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
  86     id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute Register 6")
  87
  88     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  89
  90     # [31:0] is implementation defined
  91     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  92         "AArch64 Auxiliary Feature Register 0")
  93     # Reserved for future expansion
  94     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  95         "AArch64 Auxiliary Feature Register 1")
  96
  97     # 1 CTX CMPs | 16 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
  98     id_aa64dfr0_el1 = Param.UInt64(0x0000000000F0F006,
  99         "AArch64 Debug Feature Register 0")
 100     # Reserved for future expansion
 101     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
 102         "AArch64 Debug Feature Register 1")
 103
 104     # !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
 105     id_aa64isar0_el1 = Param.UInt64(0x0000000010000000,
 106         "AArch64 Instruction Set Attribute Register 0")
 107
 108     # !I8MM | !BF16 | SPECRES = 0 | !SB |
 109     # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
 110     id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
 111         "AArch64 Instruction Set Attribute Register 1")
 112
 113     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 114     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 115         "AArch64 Memory Model Feature Register 0")
 116     # PAN | HPDS | !VHE
 117     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
 118         "AArch64 Memory Model Feature Register 1")
 119     # |VARANGE
 120     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010000,
 121         "AArch64 Memory Model Feature Register 2")
 122
 123     # Any access (read/write) to an unimplemented
 124     # Implementation Defined registers is not causing an Undefined Instruction.
 125     # It is rather executed as a NOP.
 126     impdef_nop = Param.Bool(False,
 127         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
 128
 129     # This is required because in SE mode a generic System SimObject is
 130     # allocated, instead of an ArmSystem
 131     sve_vl_se = Param.SveVectorLength(1,
 132         "SVE vector length in quadwords (128-bit), SE-mode only")
 133
 134     # Recurse into subnodes to generate DTB entries. This is mainly needed to
 135     # generate the PMU entry.
 136     generateDeviceTree = SimObject.recurseDeviceTree