src/arch/arm/ArmISA.py

   1 # Copyright (c) 2012-2013, 2015-2019 ARM Limited
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  35 #
  36 # Authors: Andreas Sandberg
  37 #          Giacomo Gabrielli
  38
  39 from m5.params import *
  40 from m5.proxy import *
  41 from m5.SimObject import SimObject
  42
  43 from m5.objects.ArmPMU import ArmPMU
  44 from m5.objects.ArmSystem import SveVectorLength
  45 from m5.objects.ISACommon import VecRegRenameMode
  46
  47 # Enum for DecoderFlavour
  48 class DecoderFlavour(Enum): vals = ['Generic']
  49
  50 class ArmISA(SimObject):
  51     type = 'ArmISA'
  52     cxx_class = 'ArmISA::ISA'
  53     cxx_header = "arch/arm/isa.hh"
  54
  55     system = Param.System(Parent.any, "System this ISA object belongs to")
  56
  57     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  58     decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
  59
  60     # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
  61     # When 'highest_el_is_64' (AArch64 support) is:
  62     #   True  -> Cortex-A57 TRM r0p0 MIDR is used
  63     #   False -> Cortex-A15 TRM r0p0 MIDR is used
  64     midr = Param.UInt32(0x0, "MIDR value")
  65
  66     # See section B4.1.89 - B4.1.92 of the ARM ARM
  67     #  VMSAv7 support
  68     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  69     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  70     # no HW access | WFI stalling | ISB and DSB |
  71     # all TLB maintenance | no Harvard
  72     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  73     # SuperSec | Coherent TLB | Bcast Maint |
  74     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  75     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  76
  77     # See section B4.1.84 of ARM ARM
  78     # All values are latest for ARMv7-A profile
  79     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  80     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  81     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  82     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  83     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  84     id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
  85
  86     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  87
  88     # [31:0] is implementation defined
  89     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  90         "AArch64 Auxiliary Feature Register 0")
  91     # Reserved for future expansion
  92     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  93         "AArch64 Auxiliary Feature Register 1")
  94
  95     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
  96     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
  97         "AArch64 Debug Feature Register 0")
  98     # Reserved for future expansion
  99     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
 100         "AArch64 Debug Feature Register 1")
 101
 102     # !CRC32 | !SHA2 | !SHA1 | !AES
 103     id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
 104         "AArch64 Instruction Set Attribute Register 0")
 105     # Reserved for future expansion
 106     id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
 107         "AArch64 Instruction Set Attribute Register 1")
 108
 109     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 110     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 111         "AArch64 Memory Model Feature Register 0")
 112     # PAN | HPDS
 113     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
 114         "AArch64 Memory Model Feature Register 1")
 115     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 116         "AArch64 Memory Model Feature Register 2")
 117
 118     # Any access (read/write) to an unimplemented
 119     # Implementation Defined registers is not causing an Undefined Instruction.
 120     # It is rather executed as a NOP.
 121     impdef_nop = Param.Bool(False,
 122         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
 123
 124     # This is required because in SE mode a generic System SimObject is
 125     # allocated, instead of an ArmSystem
 126     sve_vl_se = Param.SveVectorLength(1,
 127         "SVE vector length in quadwords (128-bit), SE-mode only")