src/arch/arm/ArmISA.py

   1 # Copyright (c) 2012-2013, 2015 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
  17 # redistributions in binary form must reproduce the above copyright
  18 # notice, this list of conditions and the following disclaimer in the
  19 # documentation and/or other materials provided with the distribution;
  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Sandberg
  37 #          Giacomo Gabrielli
  38
  39 from m5.params import *
  40 from m5.proxy import *
  41 from m5.SimObject import SimObject
  42
  43 from ArmPMU import ArmPMU
  44
  45 # Enum for DecoderFlavour
  46 class DecoderFlavour(Enum): vals = ['Generic']
  47
  48 class ArmISA(SimObject):
  49     type = 'ArmISA'
  50     cxx_class = 'ArmISA::ISA'
  51     cxx_header = "arch/arm/isa.hh"
  52
  53     system = Param.System(Parent.any, "System this ISA object belongs to")
  54
  55     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  56     decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
  57
  58     midr = Param.UInt32(0x410fc0f0, "MIDR value")
  59
  60     # See section B4.1.93 - B4.1.94 of the ARM ARM
  61     #
  62     # !ThumbEE | !Jazelle | Thumb | ARM
  63     # Note: ThumbEE is disabled for now since we don't support CP14
  64     # config registers and jumping to ThumbEE vectors
  65     id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
  66     # !Timer | Virti | !M Profile | TrustZone | ARMv4
  67     id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1")
  68
  69     # See section B4.1.89 - B4.1.92 of the ARM ARM
  70     #  VMSAv7 support
  71     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  72     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  73     # no HW access | WFI stalling | ISB and DSB |
  74     # all TLB maintenance | no Harvard
  75     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  76     # SuperSec | Coherent TLB | Bcast Maint |
  77     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  78     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  79
  80     # See section B4.1.84 of ARM ARM
  81     # All values are latest for ARMv7-A profile
  82     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  83     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  84     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  85     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  86     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  87     id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
  88
  89     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  90
  91     # [31:0] is implementation defined
  92     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  93         "AArch64 Auxiliary Feature Register 0")
  94     # Reserved for future expansion
  95     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  96         "AArch64 Auxiliary Feature Register 1")
  97
  98     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
  99     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
 100         "AArch64 Debug Feature Register 0")
 101     # Reserved for future expansion
 102     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
 103         "AArch64 Debug Feature Register 1")
 104
 105     # !CRC32 | !SHA2 | !SHA1 | !AES
 106     id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
 107         "AArch64 Instruction Set Attribute Register 0")
 108     # Reserved for future expansion
 109     id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
 110         "AArch64 Instruction Set Attribute Register 1")
 111
 112     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 113     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 114         "AArch64 Memory Model Feature Register 0")
 115     # Reserved for future expansion
 116     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
 117         "AArch64 Memory Model Feature Register 1")
 118
 119     # !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
 120     # (no AArch32/64 interprocessing support for now)
 121     id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
 122         "AArch64 Processor Feature Register 0")
 123     # Reserved for future expansion
 124     id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
 125         "AArch64 Processor Feature Register 1")