src/arch/arm/ArmISA.py

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  35 #
  36 # Authors: Andreas Sandberg
  37 #          Giacomo Gabrielli
  38
  39 from m5.params import *
  40 from m5.proxy import *
  41
  42 from m5.objects.ArmPMU import ArmPMU
  43 from m5.objects.ArmSystem import SveVectorLength
  44 from m5.objects.BaseISA import BaseISA
  45 from m5.objects.ISACommon import VecRegRenameMode
  46
  47 # Enum for DecoderFlavor
  48 class DecoderFlavor(Enum): vals = ['Generic']
  49
  50 class ArmISA(BaseISA):
  51     type = 'ArmISA'
  52     cxx_class = 'ArmISA::ISA'
  53     cxx_header = "arch/arm/isa.hh"
  54
  55     system = Param.System(Parent.any, "System this ISA object belongs to")
  56
  57     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  58     decoderFlavor = Param.DecoderFlavor(
  59             'Generic', "Decoder flavor specification")
  60
  61     # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
  62     # When 'highest_el_is_64' (AArch64 support) is:
  63     #   True  -> Cortex-A57 TRM r0p0 MIDR is used
  64     #   False -> Cortex-A15 TRM r0p0 MIDR is used
  65     midr = Param.UInt32(0x0, "MIDR value")
  66
  67     # See section B4.1.89 - B4.1.92 of the ARM ARM
  68     #  VMSAv7 support
  69     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  70     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  71     # no HW access | WFI stalling | ISB and DSB |
  72     # all TLB maintenance | no Harvard
  73     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  74     # SuperSec | Coherent TLB | Bcast Maint |
  75     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  76     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  77
  78     # See section B4.1.84 of ARM ARM
  79     # All values are latest for ARMv7-A profile
  80     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  81     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  82     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  83     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  84     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  85     id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
  86
  87     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  88
  89     # [31:0] is implementation defined
  90     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  91         "AArch64 Auxiliary Feature Register 0")
  92     # Reserved for future expansion
  93     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  94         "AArch64 Auxiliary Feature Register 1")
  95
  96     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
  97     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
  98         "AArch64 Debug Feature Register 0")
  99     # Reserved for future expansion
 100     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
 101         "AArch64 Debug Feature Register 1")
 102
 103     # !CRC32 | !SHA2 | !SHA1 | !AES
 104     id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
 105         "AArch64 Instruction Set Attribute Register 0")
 106
 107     # GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1
 108     id_aa64isar1_el1 = Param.UInt64(0x0000000001000010,
 109         "AArch64 Instruction Set Attribute Register 1")
 110
 111     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 112     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 113         "AArch64 Memory Model Feature Register 0")
 114     # PAN | HPDS
 115     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
 116         "AArch64 Memory Model Feature Register 1")
 117     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 118         "AArch64 Memory Model Feature Register 2")
 119
 120     # Any access (read/write) to an unimplemented
 121     # Implementation Defined registers is not causing an Undefined Instruction.
 122     # It is rather executed as a NOP.
 123     impdef_nop = Param.Bool(False,
 124         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
 125
 126     # This is required because in SE mode a generic System SimObject is
 127     # allocated, instead of an ArmSystem
 128     sve_vl_se = Param.SveVectorLength(1,
 129         "SVE vector length in quadwords (128-bit), SE-mode only")