src/arch/arm/ArmISA.py

   1 # Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
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  14 # modification, are permitted provided that the following conditions are
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Sandberg
  37 #          Giacomo Gabrielli
  38
  39 from m5.params import *
  40 from m5.proxy import *
  41 from m5.SimObject import SimObject
  42
  43 from ArmPMU import ArmPMU
  44 from ISACommon import VecRegRenameMode
  45
  46 # Enum for DecoderFlavour
  47 class DecoderFlavour(Enum): vals = ['Generic']
  48
  49 class ArmISA(SimObject):
  50     type = 'ArmISA'
  51     cxx_class = 'ArmISA::ISA'
  52     cxx_header = "arch/arm/isa.hh"
  53
  54     system = Param.System(Parent.any, "System this ISA object belongs to")
  55
  56     pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
  57     decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
  58
  59     midr = Param.UInt32(0x410fc0f0, "MIDR value")
  60
  61     # See section B4.1.89 - B4.1.92 of the ARM ARM
  62     #  VMSAv7 support
  63     id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
  64     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
  65     # no HW access | WFI stalling | ISB and DSB |
  66     # all TLB maintenance | no Harvard
  67     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
  68     # SuperSec | Coherent TLB | Bcast Maint |
  69     # BP Maint | Cache Maint Set/way | Cache Maint MVA
  70     id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
  71
  72     # See section B4.1.84 of ARM ARM
  73     # All values are latest for ARMv7-A profile
  74     id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
  75     id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
  76     id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
  77     id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
  78     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
  79     id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
  80
  81     fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
  82
  83     # [31:0] is implementation defined
  84     id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
  85         "AArch64 Auxiliary Feature Register 0")
  86     # Reserved for future expansion
  87     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
  88         "AArch64 Auxiliary Feature Register 1")
  89
  90     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
  91     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
  92         "AArch64 Debug Feature Register 0")
  93     # Reserved for future expansion
  94     id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
  95         "AArch64 Debug Feature Register 1")
  96
  97     # !CRC32 | !SHA2 | !SHA1 | !AES
  98     id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
  99         "AArch64 Instruction Set Attribute Register 0")
 100     # Reserved for future expansion
 101     id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
 102         "AArch64 Instruction Set Attribute Register 1")
 103
 104     # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
 105     id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
 106         "AArch64 Memory Model Feature Register 0")
 107     # Reserved for future expansion
 108     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
 109         "AArch64 Memory Model Feature Register 1")
 110     id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
 111         "AArch64 Memory Model Feature Register 2")
 112
 113     # Any access (read/write) to an unimplemented
 114     # Implementation Defined registers is not causing an Undefined Instruction.
 115     # It is rather executed as a NOP.
 116     impdef_nop = Param.Bool(False,
 117         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")