2 # Copyright (c) 2009-2014, 2017 ARM Limited
5 # The license below extends only to copyright in the software and shall
6 # not be construed as granting a license to any other intellectual
7 # property including but not limited to intellectual property relating
8 # to a hardware implementation of the functionality of the software
9 # licensed hereunder. You may use the software subject to the license
10 # terms below provided that you ensure that this notice is replicated
11 # unmodified and in its entirety in all distributions of the software,
12 # modified or unmodified, in source code or in binary form.
14 # Redistribution and use in source and binary forms, with or without
15 # modification, are permitted provided that the following conditions are
16 # met: redistributions of source code must retain the above copyright
17 # notice, this list of conditions and the following disclaimer;
18 # redistributions in binary form must reproduce the above copyright
19 # notice, this list of conditions and the following disclaimer in the
20 # documentation and/or other materials provided with the distribution;
21 # neither the name of the copyright holders nor the names of its
22 # contributors may be used to endorse or promote products derived from
23 # this software without specific prior written permission.
25 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 # Authors: Matt Horsnell
40 from m5
.defines
import buildEnv
41 from m5
.SimObject
import *
42 from m5
.params
import *
43 from m5
.params
import isNullPointer
44 from m5
.proxy
import *
46 class ProbeEvent(object):
47 def __init__(self
, pmu
, _eventId
, obj
, *listOfNames
):
49 self
.names
= listOfNames
50 self
.eventId
= _eventId
55 for name
in self
.names
:
56 self
.pmu
.getCCObject().addEventProbe(self
.eventId
,
57 self
.obj
.getCCObject(), name
)
59 class SoftwareIncrement(object):
60 def __init__(self
,pmu
, _eventId
):
61 self
.eventId
= _eventId
65 self
.pmu
.getCCObject().addSoftwareIncrementEvent(self
.eventId
)
67 ARCH_EVENT_CORE_CYCLES
= 0x11
69 class ArmPMU(SimObject
):
72 cxx_class
= 'ArmISA::PMU'
73 cxx_header
= 'arch/arm/pmu.hh'
76 PyBindMethod("addEventProbe"),
77 PyBindMethod("addSoftwareIncrementEvent"),
82 def addEvent(self
, newObject
):
83 if not (isinstance(newObject
, ProbeEvent
)
84 or isinstance(newObject
, SoftwareIncrement
)):
85 raise TypeError("argument must be of ProbeEvent or "
86 "SoftwareIncrement type")
91 self
._events
.append(newObject
)
93 # Override the normal SimObject::regProbeListeners method and
94 # register deferred event handlers.
95 def regProbeListeners(self
):
96 for event
in self
._events
:
99 self
.getCCObject().regProbeListeners()
101 def addArchEvents(self
,
104 icache
=None, dcache
=None,
106 """Add architected events to the PMU.
108 This method can be called multiple times with only a subset of
109 the keyword arguments set. This enables event registration in
110 configuration scripts to happen closer to the instantiation of
111 the instrumented objects (e.g., the memory system) instead of
114 CPU events should also be registered once per CPU that is
115 sharing the PMU (e.g., when switching between CPU models).
118 bpred
= cpu
.branchPred
if cpu
and not isNullPointer(cpu
.branchPred
) \
121 self
.addEvent(SoftwareIncrement(self
,0x00))
122 # 0x01: L1I_CACHE_REFILL
123 self
.addEvent(ProbeEvent(self
,0x02, itb
, "Refills"))
124 # 0x03: L1D_CACHE_REFILL
126 self
.addEvent(ProbeEvent(self
,0x05, dtb
, "Refills"))
127 self
.addEvent(ProbeEvent(self
,0x06, cpu
, "RetiredLoads"))
128 self
.addEvent(ProbeEvent(self
,0x07, cpu
, "RetiredStores"))
129 self
.addEvent(ProbeEvent(self
,0x08, cpu
, "RetiredInsts"))
132 # 0x0B: CID_WRITE_RETIRED
133 self
.addEvent(ProbeEvent(self
,0x0C, cpu
, "RetiredBranches"))
134 # 0x0D: BR_IMMED_RETIRED
135 # 0x0E: BR_RETURN_RETIRED
136 # 0x0F: UNALIGEND_LDST_RETIRED
137 self
.addEvent(ProbeEvent(self
,0x10, bpred
, "Misses"))
138 self
.addEvent(ProbeEvent(self
, ARCH_EVENT_CORE_CYCLES
, cpu
,
140 self
.addEvent(ProbeEvent(self
,0x12, bpred
, "Branches"))
141 self
.addEvent(ProbeEvent(self
,0x13, cpu
, "RetiredLoads",
146 # 0x17: L2D_CACHE_REFILL
151 # 0x1C: TTBR_WRITE_RETIRED
154 # 0x1F: L1D_CACHE_ALLOCATE
155 # 0x20: L2D_CACHE_ALLOCATE
157 # 0x22: BR_MIS_PRED_RETIRED
158 # 0x23: STALL_FRONTEND
159 # 0x24: STALL_BACKEND
163 # 0x28: L2I_CACHE_REFILL
164 # 0x29: L3D_CACHE_ALLOCATE
165 # 0x2A: L3D_CACHE_REFILL
168 # 0x2D: L2D_TLB_REFILL
169 # 0x2E: L2I_TLB_REFILL
173 cycleEventId
= Param
.Int(ARCH_EVENT_CORE_CYCLES
, "Cycle event id")
174 platform
= Param
.Platform(Parent
.any
, "Platform this device is part of.")
175 eventCounters
= Param
.Int(31, "Number of supported PMU counters")
176 pmuInterrupt
= Param
.Int(68, "PMU GIC interrupt number")