src/arch/arm/ArmSystem.py

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  35
  36 from m5.params import *
  37 from m5.options import *
  38 from m5.SimObject import *
  39 from m5.util.fdthelper import *
  40
  41 from m5.objects.System import System
  42 from m5.objects.ArmSemihosting import ArmSemihosting
  43
  44 class SveVectorLength(UInt8): min = 1; max = 16
  45
  46 class ArmSystem(System):
  47     type = 'ArmSystem'
  48     cxx_header = "arch/arm/system.hh"
  49     multi_proc = Param.Bool(True, "Multiprocessor system?")
  50     gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
  51     flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
  52     have_security = Param.Bool(False,
  53         "True if Security Extensions are implemented")
  54     have_virtualization = Param.Bool(False,
  55         "True if Virtualization Extensions are implemented")
  56     have_crypto = Param.Bool(False,
  57         "True if Crypto Extensions is implemented")
  58     have_lpae = Param.Bool(True, "True if LPAE is implemented")
  59     reset_addr = Param.Addr(0x0,
  60         "Reset address (ARMv8)")
  61     auto_reset_addr = Param.Bool(True,
  62         "Determine reset address from kernel entry point if no boot loader")
  63     highest_el_is_64 = Param.Bool(False,
  64         "True if the register width of the highest implemented exception level "
  65         "is 64 bits (ARMv8)")
  66     phys_addr_range_64 = Param.UInt8(40,
  67         "Supported physical address range in bits when using AArch64 (ARMv8)")
  68     have_large_asid_64 = Param.Bool(False,
  69         "True if ASID is 16 bits in AArch64 (ARMv8)")
  70     have_sve = Param.Bool(True,
  71         "True if SVE is implemented (ARMv8)")
  72     sve_vl = Param.SveVectorLength(1,
  73         "SVE vector length in quadwords (128-bit)")
  74     have_lse = Param.Bool(True,
  75         "True if LSE is implemented (ARMv8.1)")
  76     have_pan = Param.Bool(True,
  77         "True if Priviledge Access Never is implemented (ARMv8.1)")
  78
  79     semihosting = Param.ArmSemihosting(NULL,
  80         "Enable support for the Arm semihosting by settings this parameter")
  81
  82     m5ops_base = Param.Addr(0,
  83         "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
  84         "to disable.")
  85
  86     # Set to true if simulation provides a PSCI implementation
  87     # This flag will be checked when auto-generating
  88     # a PSCI node. A client (e.g Linux) would then be able to
  89     # know if it can use the PSCI APIs
  90     _have_psci = False
  91
  92     def generateDtb(self, filename):
  93         """
  94         Autogenerate DTB. Arguments are the folder where the DTB
  95         will be stored, and the name of the DTB file.
  96         """
  97         state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
  98         rootNode = self.generateDeviceTree(state)
  99
 100         fdt = Fdt()
 101         fdt.add_rootnode(rootNode)
 102         fdt.writeDtbFile(filename)
 103
 104
 105     def generateDeviceTree(self, state):
 106         # Generate a device tree root node for the system by creating the root
 107         # node and adding the generated subnodes of all children.
 108         # When a child needs to add multiple nodes, this is done by also
 109         # creating a node called '/' which will then be merged with the
 110         # root instead of appended.
 111
 112         def generateMemNode(mem_range):
 113             node = FdtNode("memory@%x" % long(mem_range.start))
 114             node.append(FdtPropertyStrings("device_type", ["memory"]))
 115             node.append(FdtPropertyWords("reg",
 116                 state.addrCells(mem_range.start) +
 117                 state.sizeCells(mem_range.size()) ))
 118             return node
 119
 120         root = FdtNode('/')
 121         root.append(state.addrCellsProperty())
 122         root.append(state.sizeCellsProperty())
 123
 124         # Add memory nodes
 125         for mem_range in self.mem_ranges:
 126             root.append(generateMemNode(mem_range))
 127
 128         for node in self.recurseDeviceTree(state):
 129             # Merge root nodes instead of adding them (for children
 130             # that need to add multiple root level nodes)
 131             if node.get_name() == root.get_name():
 132                 root.merge(node)
 133             else:
 134                 root.append(node)
 135
 136         return root